Multilayer antifuse with intermediate spacer layer

An antifuse structure having a first insulating layer on a semiconductor substrate in an integrated circuit comprising:

• a first metal interconnection line;
• a sacrificial layer formed on said first metal interconnection line, said sacrificial layer having a first thickness;
• a second insulating layer formed on said sacrificial layer;
• an aperture having a bottom and sides through said second insulating layer, said bottom being concave and having sloped edge portions and a relatively flat center portion wherein said antifuse is to be located, said sloped edge portions defining sacrificial layer edge portions located between said sides and said relatively flat center portion, and said relatively flat center portion defining a first metal interconnection line portion located between said sloped edge portions;
• a programming layer on said second insulating layer, said sides, and said bottom, said programming layer having a second thickness that is substantially uniform along said bottom, and said programming layer and said sacrificial layer being of different materials;
• and
• a second metal interconnection line on said programming layer;
• and
• whereby a thickness of said programming layer at said relatively flat center portion is much thinner than a combined thickness of said programming layer and said sacrificial layer at said sloped edge portions.