Semiconductor device having an improved packing density and high reliability
AssigneeSamsung Electronics Co., Ltd.
InventorsKyu-pil Lee, Yong-jik Park
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AssigneeSamsung Electronics Co., Ltd.
InventorsKyu-pil Lee, Yong-jik Park
Estimating the term…
A semiconductor device is fabricated having contact holes formed in an interlayer insulator and on impurity diffusion regions positioned on either side of an isolator, The contact holes are arranged so as not to be disposed along a shortest line path across the isolator. This arrangement isolating interval and provides a structure which can realize higher packing density and improved reliability.
A semiconductor device having contact holes selectively formed thereon comprising:
A semiconductor device having contact holes selectively formed thereon comprising:
Dependencies are inferred from the claim text.
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Interconnections in chips, wafers or substrates: interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or…
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Generic packages, interconnections, connectors or other constructional details of devices covered by
Electronic memory devices
Term ended 16 Apr 2013 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to a semiconductor device in which there is formed a contact hole in a manner resulting in a structure having an improved packing density and high reliability.
2. Description of the Prior Art
The above objects and other advantages of the present invention will become more apparent by describing in detail a preferred embodiment of the present invention with reference to the attached drawings in which:
FIG. 1A illustrates a layout of a semiconductor device which shows a conventional method for forming a contact hole in a semiconductor device;
FIG. 1B is a cross section of the semiconductor device of FIG. 1A cut along line 1B--1B;
In the following figures now to be explained in greater detail, like reference numerals as those in FIGS. 1A and 1B are used to represent like components.
FIG. 2A shows a layout where mask patterns P2 forming contact holes are not located along a shortest line distance across a field oxide layer. L.sub.12 represents a shortest distance between contact holes, L.sub.10 represents the shortest distance from the contact hole (field oxide layer side) to the edge of the field oxide layer, and .theta. represents the angle between a shortest horizontal line distance connecting contact holes and a shortest distance across the field oxide layer.
In FIG. 2A, because shortest distance L between contact holes is lengthened by ##EQU1## compared with the shortest distance L.sub.11 of FIG. 1A, L.sub.s is increased proportionally.