Global planarization process using patterned oxide
AssigneeTexas Instruments Incorporated
InventorsDennis J. Yost, Patrick M. Martin
Life of this patent
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Abstract
A method for planarizing the surface of a layer in a semiconductor device includes forming conductor regions 24, 26, and 28 on a layer of the semiconductor device; forming first insulator regions 30, 32, and 34 in gaps between the conductor regions 24, 26, and 28; and forming an insulator layer 40 over the first insulator regions 30, 32, and 34, and over the conductor regions 24, 26, and 28 such that a surface of the insulator layer 40 will be substantially planar.
Claims13
A method for planarizing a surface of a layer in a semiconductor device comprising:
- forming conductor regions on a layer of the semiconductor device;
- forming a first insulator layer over and between the conductor regions;
- etching the first insulator layer to form insulator regions between the conductor regions, and forming gaps between the insulator regions and the conductor regions, and leaving portions of the first insulator layer over the conductor regions after etching;
- and
- forming a second insulator layer over the insulator regions and over the conductor regions such that a surface of the second insulator layer will be planar.
A method for planarizing a surface of a layer in a semiconductor device comprising:
- forming conductor regions on a layer of the semiconductor device;
- forming first insulator regions between the conductor regions;
- forming second insulator regions over the conductor regions and separated from the first insulator regions;
- and
- forming an insulator layer over the first and second insulator regions such that a surface of the insulator layer will be planar.
Dependencies are inferred from the claim text.