Split-gate flash memory cell
AssigneeUnited Microelectronics Corp.
InventorGary Hong
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Abstract
This patent discloses a split-gate flash memory cell having a vertical isolation gate and a process for making it. The inventive cell has better control and a denser memory array than conventional cells. By use of a vertical isolation gate a smaller cell size is obtained. The memory cell has a floating gate transistor formed in a substrate having a channel extending underneath a floating gate, and a vertical isolation transistor formed in the substrate having a channel parallel to a trench holding a portion of a polysilicon control gate and orthogonal to the channel of the floating gate transistor.
Claims19
A split gate memory cell comprising,
- a substrate of a first dopant type,
- a first oxide layer grown on a surface of said substrate,
- a trench formed in said substrate,
- a source of a second dopant type formed in said trench in said substrate,
- a drain of said second dopant type formed in said substrate near said surface,
- a floating gate deposited on said first oxide layer between said source and said drain,
- a second oxide layer grown on walls of said trench and walls of said floating gate,
- a dielectric deposited on said floating gate, and
- a control gate covering said second oxide layer and said dielectric, wherein said drain is separated from said trench by a horizontal channel length of a floating gate transistor, said source is separated from said floating gate by a vertical channel length of a vertical isolation transistor which runs parallel to a side wall of said trench, and wherein a total channel length of said cell is a sum of said horizontal and said vertical channel lengths, said total channel length being consistently controllable.
A process for fabricating a split-gate flash memory cell, comprising,
- growing a first oxide layer on a substrate having a first dopant-type,
- depositing a polysilicon layer on said first oxide layer,
- forming a dielectric on said polysilicon layer,
- patterning polysilicon floating gates out of said polysilicon layer and said first oxide layer using a mask and etch process,
- forming trenches in said substrate between every other one of said floating gates using a mask and etch process,
- growing a second oxide layer on side walls of said floating gates and said trenches,
- implanting ions of a second dopant type in said trenches and between said floating gates so that said implanted ions in said trenches are separated from said first oxide layer by a vertical channel length of a vertical isolation transistor which runs parallel to a side wall of each said trench, and said implanted ions between said floating gates are separated from said trenches by a horizontal channel length, and
- depositing a wordline over said second oxide layer and said dielectric.
A memory cell, comprising
- a floating gate transistor formed in a substrate having a channel extending horizontally underneath a floating gate,
- a vertical isolation transistor formed in said substrate having a channel parallel to a trench holding a portion of a polysilicon control gate and orthogonal to the channel of the floating gate transistor, wherein said trench is located at one side of said floating gate,
- a drain located at an opposite side from said one side of said floating gate so that said drain is separated from said trench by said channel of the floating gate transistor, and
- a source located in said trench having a width which is substantially equal to a width of said trench.
Dependencies are inferred from the claim text.