EEPROM cell with isolation transistor and methods for making and operating the same

An electrically erasable and programmable read-only memory cell comprising:

• a semiconductor substrate;
• a tunnel dielectric formed on the substrate and having a
• thickness of less than approximately 120 angstroms;
• a floating gate transistor having a source region formed in the substrate, a drain region formed in the substrate, a floating gate formed on the tunnel dielectric and approximately positioned between the source and drain regions of the floating gate transistor, and a control gate overlying the floating gate;
• and
• an isolation transistor having a source region formed in the substrate, a drain region formed in the substrate, and an isolation gate formed on the tunnel dielectric and approximately positioned between the source and drain regions of the isolation transistor;
• wherein the drain region of the isolation transistor is the source region of the floating gate transistor;
• and
• wherein the isolation gate is physically and electrically independent from the control gate of the floating gate transistor.

A method for programming an electrically erasable and programmable memory cell comprising the steps of:

• providing a memory cell comprising:
• a floating gate transistor having a source and a drain, a floating gate, and a control gate;
• and
• an isolation transistor having a source and a drain and an isolation gate;
• wherein the drain of the isolation transistor is coupled to the source of the floating gate transistor;
• and
• wherein the isolation gate is physically and electrically independent from the control gate of the floating gate transistor;
• applying a voltage to the isolation gate of the isolation transistor;
• applying the voltage to the source of the isolation transistor;
• applying a first programming voltage to the control gate of the floating gate transistor which is high relative to the voltage;
• and applying a second programming voltage to the drain of the floating gate transistor which is high relative to the voltage.

A method for programming a flash electrically erasable and programmable memory cell comprising the steps of:

• providing a memory cell comprising:
• a floating gate transistor having a source and a drain, a floating gate, and a control gate;
• and
• an isolation transistor having a source and a drain and an isolation gate;
• wherein the drain of the isolation transistor is coupled to the source of the floating gate transistor;
• wherein the floating gate and isolation gate are formed on a tunnel dielectric having a thickness of less than approximately 120 angstroms;
• and
• wherein the isolation gate is physically and electrically independent from the control gate of the floating gate transistor;
• applying a voltage to the isolation gate of the isolation transistor;
• applying the voltage to the source of the isolation transistor;
• applying a first programming voltage to the control gate of the floating gate transistor which is low relative to the voltage;
• and
• applying a second programming voltage to the drain the floating gate transistor which is high relative to the voltage.

An electrically erasable and programmable read-only memory cell comprising:

• a semiconductor substrate;
• a gate dielectric formed on the semiconductor substrate and having a substantially uniform thickness of less than approximately 120 angstroms within the memory cell;
• a floating gate electrode formed on the gate dielectric;
• an isolation gate electrode formed on the gate dielectric and spaced apart from the floating gate electrode;
• a first doped region formed in the semiconductor substrate and approximately aligned to a first edge of the isolation gate electrode;
• a second doped region formed in the semiconductor substrate, between the isolation gate electrode and the floating gate electrode, and approximately aligned to a second edge of the isolation gate electrode and a first edge of the floating gate electrode;
• a third doped region formed in the semiconductor substrate and approximately aligned to a second edge of the floating gate electrode;
• an interlayer dielectric formed over the floating gate electrode and over the isolation gate electrode;
• and
• a control gate electrode formed over the interlayer dielectric and over the floating gate electrode;
• wherein the isolation gate electrode, the first doped region, and the second doped region form an isolation transistor of the memory cell;
• and
• wherein the floating gate electrode, the second doped region, the third doped region, and the control gate electrode form a floating gate transistor of the memory cell.