Semiconductor device with vertical transistors connected in series between bit lines

A semiconductor memory device comprising:

• a plurality of word lines;
• a plurality of bit lines crossing said word lines;
• a plurality of memory cells provided at intersections of said word lines and said bit lines;
• and
• a row decoder for selecting a specified one of said word lines, the row decoder comprising a transistor, the transistor including
• a semiconductor substrate,
• a plurality of semiconductor columns formed on said semiconductor substrate with a predetermined distance in predetermined directions,
• an insulated gate electrode formed around a side wall of each of said semiconductor columns,
• a first diffusion layer functioning as one of a source and a drain, said first diffusion layer being formed at a top portion of one endmost one of said semiconductor columns and connected to said specified word line,
• a second diffusion layer functioning as one of a source and a drain, said second diffusion layer being formed at a top portion of the other endmost one of said semiconductor columns and connected to a power supply line, and
• a diffusion layer functioning as another of the source and the drain, wherein said diffusion layer is formed between adjacent ones of said semiconductor columns at bottom portions and peripheral portions of said bottom portions of said adjacent ones of semiconductor columns, is shared by said adjacent semiconductor columns and is not connected to any external wiring.

A semiconductor memory device comprising:

• a plurality of memory cells arranged in a matrix;
• a first bit line connected to a one of said memory cells;
• a second bit line connected to a dummy memory cell which is paired with said one of memory cells;
• and
• a sense amplifier, connected to said first bit line and said second bit line and having a transistor, for amplifying a potential difference between said first bit line and said second bit line,
• wherein said transistor includes,
• a semiconductor substrate,
• a first group of semiconductor columns formed linearly on said semiconductor substrate at predetermined intervals,
• a second group of semiconductor columns formed with a predetermined distance set from said first group of semiconductor columns,
• a first gate electrode formed to extend from a side wall of one of said first group of semiconductor columns, said one of said first group of semiconductor columns being adjacent to an endmost one of said first group of semiconductor columns, to a top portion of said endmost one of the first group of semiconductor columns with an insulating layer interposed, said first gate electrode being connected to said second bit line at said top portion of the endmost one of the first group of semiconductor columns,
• a second gate electrode formed to extend from a side wall of one of said second group of semiconductor columns, said one of said second group of semiconductor columns being adjacent to an endmost one of the second group of semiconductor columns, to a top portion of said endmost one of the second group of semiconductor columns with an insulating layer interposed, said second gate electrode being connected to said first bit line at said top portion of said endmost one of the second group of semiconductor columns, and
• a diffusion layer functioning as one of a source and a drain, said diffusion layer being shared by bottom portions of adjacent ones of said semiconductor columns of said first and second groups which are arranged linearly, wherein said diffusion layer is not connected to any external wiring.

A semiconductor memory device comprising:

• a plurality of memory cells arranged in a matrix;
• a first bit line connected to a one of said memory cells;
• a second bit line connected to another of said memory cells;
• and
• an equalizer connected to said first bit line and said second bit line and having a transistor, for equalizing potentials of said first bit line and said second bit line,
• wherein said transistor further includes,
• a semiconductor substrate,
• a first semiconductor column formed on said semiconductor substrate,
• a second semiconductor column formed on said semiconductor substrate with a predetermined distance set from said first semiconductor column,
• a first gate electrode formed around a side wall of said first semiconductor column with an insulating layer interposed,
• a second gate electrode formed around a side wall of said second semiconductor column with an insulating layer interposed, said second gate electrode being electrically connected to said first gate electrode,
• a first diffusion layer being formed at a top portion of said first semiconductor column and connected to said first bit line,
• a second diffusion layer being formed at a top portion of said second semiconductor column and connected to said second bit line, and
• a diffusion layer functioning as one of a source and a drain, said diffusion layer being shared by bottom portions of said first and second semiconductor columns without being connected to any external wiring.

A semiconductor memory device comprising:

• a plurality of memory cells arranged in a matrix;
• a first bit line connected to a one of said memory cells;
• a second bit line connected to another of said memory cells;
• and
• a sense amplifier with two inputs, connected to said first bit line and said second bit line and having first and second transistors, for amplifying a potential difference between said first bit line and said second bit line, a first transistor connecting a first input of said two inputs to said first bit line, a second transistor connecting a second input of said two inputs to said second bit line,
• wherein said first transistor includes,
• a semiconductor substrate,
• a first semiconductor column formed on said semiconductor substrate,
• a second semiconductor column formed on said semiconductor substrate with a predetermined distance set from said first semiconductor column,
• a first gate electrode formed around a side wall of said first semiconductor column with an insulating layer interposed,
• a second gate electrode formed around a side wall of said second semiconductor column with an insulating layer interposed, said second gate electrode being electrically connected to said first gate electrode,
• a first diffusion layer being formed at a top portion of said first semiconductor column and connected to said first bit line,
• a second diffusion layer being formed at a top portion of said second semiconductor column and connected to said first input, and
• a fifth diffusion layer functioning as one of a source and a drain, said fifth diffusion layer being shared by bottom portions of said first and second semiconductor columns without being connected to any external wiring, and
• wherein said second transistor includes,
• a semiconductor substrate,
• a third semiconductor column formed on said semiconductor substrate,
• a fourth semiconductor column formed on said semiconductor substrate with a predetermined distance set from said third semiconductor column,
• a third gate electrode formed around a side wall of said third semiconductor column with an insulating layer interposed,
• a fourth gate electrode formed around a side wall of said fourth semiconductor column with an insulating layer interposed, said fourth gate electrode being electrically connected to said third gate electrode,
• a third diffusion layer being formed at a top portion of said third semiconductor column and connected to said second bit line,
• a fourth diffusion layer being formed at a top portion of said fourth semiconductor column and connected to said second input, and
• a sixth diffusion layer functioning as one of a source and a drain, said sixth diffusion layer being shared by bottom portions of first and second semiconductor columns without being connected to any external wiring.

A semiconductor memory device comprising:

• a plurality of memory cells arranged in a matrix;
• a first bit line connected to a one of said memory cells;
• a second bit line connected to another of said memory cells;
• and
• an equalizer connected to said first bit line and said second bit line and having a transistor, for equalizing potentials of said first bit line and said second bit line,
• wherein said transistor includes,
• a semiconductor substrate,
• a first semiconductor column formed on said semiconductor substrate,
• a second semiconductor column formed on said semiconductor substrate with a predetermined distance set from said first semiconductor column,
• a third semiconductor column formed on said semiconductor substrate,
• a fourth semiconductor column formed on said semiconductor substrate with a predetermined distance set from said third semiconductor column,
• a first gate electrode formed around a side wall of said first semiconductor column with an insulating layer interposed,
• a second gate electrode formed around a side wall of said second semiconductor column with an insulating layer interposed, said second gate electrode being electrically connected to said first gate electrode,
• a first diffusion layer being formed at a top portion of said first semiconductor column and connected to said first bit line,
• a second diffusion layer being formed at a top portion of said second semiconductor column and connected to a wiring with equalized potential of said first and second bit lines,
• a fifth diffusion layer functioning as one of a source and a drain, said fifth diffusion layer being shared by bottom portions of said first and second semiconductor columns without being connected to any external wiring,
• a third gate electrode formed around a side wall of said third semiconductor column with an insulating layer interposed,
• a fourth gate electrode formed around a side wall of said fourth gate electrode being electrically connected to said third gate electrode,
• a third diffusion layer being formed at a top portion of said third semiconductor column and connected to said second bit line,
• a fourth diffusion layer being formed at a top portion of said fourth semiconductor column and connected to a wiring with equalized potential of said first and second bit lines, and
• a sixth diffusion layer functioning as one of a source and a drain, said sixth diffusion layer being shared by bottom portions of said third and fourth semiconductor columns without being connected to any external wiring.

A semiconductor device connecting between a first wiring line and a second wiring line, the device comprising:

• a semiconductor substrate;
• a first semiconductor column structured with a feature size formed on said semiconductor substrate;
• a second semiconductor column structured with the feature size, formed on said semiconductor substrate a distance of the feature size away from said first semiconductor column;
• a first gate electrode formed around a side wall of said first semiconductor column with an insulating layer interposed;
• a second gate electrode formed around a side wall of said second semiconductor column with an insulating layer interposed;
• a first diffusion layer functioning as one of a source and drain, said first diffusion layer being formed at a top portion of said first semiconductor column and connected to said first wiring line;
• a second diffusion layer functioning as another of the source and the drain, said second diffusion layer being formed at a top portion of said second semiconductor column and connected to said second wiring line;
• and
• a third diffusion layer functioning as one of a source and a drain for said first semiconductor column and functioning as another of a source and drain for said second semiconductor column, said third diffusion layer being formed at bottom portions and peripheral portions of said bottom portions of said first and second semiconductor columns shared by said first and second semiconductor columns.