High-density nonvolatile semiconductor memory
AssigneeOki Electric Industry Co., Ltd.
InventorTakashi Ono
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Abstract
A nonvolatile semiconductor memory has active regions that form parallel strips extending in a first direction in a semiconductor substrate. Each active region has source areas, drain areas, and channel areas for a series of memory cells. Floating gates are formed over the channel areas, and control gates over the floating gates. The upper surfaces of the control gates and the sides of the control gates and floating gates are covered by insulating films. Source interconnecting lines made of a conductive material are formed as parallel strips extending in a second direction different from the first direction on the semiconductor substrate, interconnecting the source areas of the memory cells.
Claims12
A nonvolatile semiconductor memory device having a plurality of memory cells, each of said memory cells having a floating gate, a control gate, a source and a drain, said device comprising:
- a semiconductor substrate:
- a plurality of active regions formed in said semiconductor substrate as parallel strips extending in a first direction and arranged separately from one another, each of said active regions having said sources, said drains, and having channels which are arranged between said sources and said drains;
- said plurality of floating gates being formed over respective channels;
- a plurality of control gate lines extending in a second direction different from said first direction, each of said control gate lines having said plurality of control gates formed over respective floating gates;
- a plurality of insulating films covering upper surface of respective control gate lines and sides of respective control gate lines and floating gates;
- and
- a plurality of source interconnecting lines formed on said semiconductor substrate and a portion of said insulating films as parallel strips of a conductive material, extending in said second direction, for interconnecting said sources arranged in different active regions.
A nonvolatile semiconductor memory device comprising:
- a semiconductor substrate;
- a first active region formed in said semiconductor substrate extending in a first direction, said first active region having a first source, a first drain, a second drain, a first channel and a second channel, wherein said first channel is formed between said first source and said first drain and said second channel is formed between said first source and said second drain;
- a second active region formed in said semiconductor substrate extending in said first direction, said first and second active regions being formed separately from each other, said second active region having a second source, a third drain, a fourth drain, a third channel and a fourth channel, wherein said third channel is formed between said second source and said third drain, and said fourth channel is formed between said second source and said fourth drain;
- first to fourth floating gates respectively formed over said first to fourth channels;
- a first control gate line extending in a second direction from said first direction, said first control gate line including a first control gate formed over said first floating gate and a second control gate formed over said third floating gate;
- a second control gate line extending in said second direction, said second control gate line including a third control gate formed over said second floating gate and a fourth control gate formed over said fourth floating gate;
- an insulating film covering upper surfaces of said first and second control gate lines and sides of said first and second control gate lines and said first to fourth floating gates;
- a source interconnecting line formed on said semiconductor substrate and a portion of said insulating film for interconnecting said first and second sources;
- a first drain interconnecting line formed over said first active region for interconnecting said first and second drains;
- and
- a second drain interconnecting line formed over said second active region for interconnecting said third and fourth drains.
Dependencies are inferred from the claim text.