Technique to manufacture a SOI wafer and its applications in integrated circuits manufacturing
OwnerYung-Chau Yeninventor
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Abstract
A SOI wafer is produced by employing a bonding tool set which can be repeatedly used to reduce manufacturing cost. The use of a bonding tool set enables its application in the fabrication of IC patterns on both sides of a thin semiconductor film. A new IC fabrication method called parallel process technique is developed to manufacture integrated circuits by utilizing a bonding tool set. This parallel process technique simplifies the complex IC chip fabrication in addition to the yield improvement and the reduction of cycle time.
Claims29
A technique to produce a first wafer having a structure which consists of a single crystal semiconductor film on an insulator, comprising the steps of:
- a) assembling a first bonding tool set;
- b) first bonding second wafer which provides said single crystal semiconductor film onto said bonding tool set;
- c) slicing said second wafer to result in a third wafer on said bonding tool set;
- d) lapping and polishing said third wafer to obtain said single crystal semiconductor film;
- e) bonding said first wafer onto said single crystal semiconductor film;
- f) removing said first bonding tool set.
A technique to manufacture an integrated circuit patterns on both sides of a single crystal semiconductor film on insulator, comprising the steps of:
- a) fabricating first IC patterns on first side of said semiconductor film on first bonding tool set,
- b) positioning first alignment patterns on said first bonding tool set,
- c) bonding second bonding tool set onto said semiconductor film,
- d) positioning second alignment patterns of said second bonding tool set,
- e) moving said second alignment patterns in an alignment operation with the help of said first alignment patterns,
- f) removing said first bonding tool set,
- g) fabricating second IC patterns on second side of said semiconductor film on said second bonding tool set,
- h) bonding a substrate onto said semiconductor film,
- i) removing said second bonding tool set,
- j) continuing the process to complete the IC fabrication on said first side of said semiconductor film.
A technique to manufacture integrated circuits with a parallel process technology, comprising the steps of:
- a) simultaneously fabricating each patterned layer on a thin film on a separate individual bonding tool set, followed by positioning each alignment pattern of said individual bonding tool set;
- b) bonding second processed thin film on second bonding tool set onto first processed thin film on first bonding tool set by the use of said first alignment pattern of said first bonding tool set and said second alignment pattern of said second bonding tool set,
- c) removing said second bonding tool set;
- d) positioning said first alignment pattern;
- e) bonding third processed thin film on third bonding tool set onto said second processed thin film by the use of said first alignment pattern of said first bonding tool set and third alignment pattern of said third bonding tool set;
- f) removing said third bonding tool set;
- g) repeating above bonding operation to bond an additional said each patterned layer according to a fabrication sequence to complete manufacturing.
Dependencies are inferred from the claim text.