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US 5,399,532 AGranted
Integrated circuit window etch and planarization
AssigneeAT&T Corp.
InventorsKuo-Hua Lee, Chen-Hua D. Yu
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Abstract
A method of semiconductor integrated circuit fabrication which provides a tapered window and a smoothed dielectric. A trench is made by etching through patterned photoresist into a dielectric. Then the corners of the trench are smoothed by thermal flow. Next the trench is etched downward by RIE blanket etchback. A window with tapered sides is thereby opened to the substrate and the dielectric is simultaneously smoothed.
Claims11
A method of semiconductor integrated circuit fabrication comprising:
- forming an undoped oxide dielectric upon a silicon substrate, said undopeal oxide dielectric having an etch rate;
- forming a doped dielectric having an initial thickness, upon said undoped oxide dielectric;
- said doped dielectric having an etch rate which is greater than the etch rate of said undoped oxide dielectric;
- etching said doped dielectric material without exposing said undoped oxide dielectric thereby forming a trench with an upper edge and a lower edge;
- smoothing said upper edge and said lower edge of said trench;
- and then
- blanket etching said doped dielectric and said undoped oxide dielectric to deepen said trench, thereby exposing said substrate at the bottom of said deepened trench,
- the said initial thickness of said doped dielectric being chosen so that a portion of said doped dielectric layer remains above said undoped oxide dielectric away from said trench after said substrate is exposed.
5 more elements
Dependencies are inferred from the claim text.