US 5,393,708 AGranted

Inter-metal-dielectric planarization process

AssigneeIndustrial Technology Research Institute

InventorsShaw-Tzeng Hsia, Kuang-Chao Chen

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Abstract

A new method of planarizing an integrated circuit is achieved. The dielectric layers between the conductive layers of an integrated circuit are formed and planarized via combining TEOS with ozone silicon oxide pyrolytic deposition with plasma-enhanced deposition processes and spin-on-glass processes. A first insulator layer is provided over the conductive layer by plasma-enhanced chemical vapor deposition (PECVD). This insulator layer is covered with a layer of TEOS with ozone deposited silicon oxide by pyrolytic chemical vapor deposition (THCVD). The TEOS with ozone silicon oxide layer will fill the irregular trenches and holes in the conductive layer structure not filled by the first insulator layer. The TEOS with ozone layer is anisotropically etched back leaving the TEOS with ozone layer only in the trenches and holes of the layer structure. A second insulating layer is deposited by PECVD and then is covered by at least one spin-on-glass layer to fill the wider valleys of the irregular structure. The spin-on-glass layer is cured, then partially blanket anisotropically etched through its thickness to the underlying second oxide layer at its highest points and leaving the spin-on-glass layer portions in the valleys. A top dielectric layer is deposited over the spin-on-glass layer to complete the planarization.

Claims20

Dependent claims

The method of planarizing the dielectric layers in the trenches and holes between conductor layers that are less than about 1.0 micron in width, in submicron integrated circuits comprising:

providing semiconductor device structures in and on a semiconductor substrate;
providing at least one patterned conductive layer for contacting the active elements of said device structures;
the surface of said patterned conductive layer structure is irregular with horizontal and vertical components forming the trenches and holes;
depositing a first layer of an insulator over said irregular structure patterned conductive layer;
covering said insulator with a layer of chemically vapor deposited silicon oxide using the TEOS with ozone pyrolytic process wherein the TEOS with ozone silicon oxide layer will partially fill said horizontal and vertical components of said layer structure not filled by said insulator layer;
anisotropically etching back said TEOS with ozone silicon oxide layer thereby leaving said TEOS with ozone layer only in said horizontal and vertical components of said layer structure and retaining a positive angle;
depositing a second insulating layer over said layer structure with said TEOS with ozone layer;
covering said second insulating layer with at least one spin-on-glass layer to fill the valleys of said irregular structure and curing said spin-on-glass layer;
partially blanket anisotropically etching said spin-on-glass layer through its thickness to the underlying said second insulating layer at its highest points and leaving said spin-on-glass layer portions in said valleys, whereby said second insulating layer prevents etching of said patterned conductive layer;
and
depositing a top dielectric layer over said spin-on-glass layer to complete said planarizing.

8 more elements

The method of planarizing the surfaces of a submicron integrated circuit without the incorporation of voids in the trenches and holes, formed by patterning a conductive layer, comprising:

providing an insulator layer over said conductive layer which connects devices within said integrated circuit wherein there are substantial surface irregularities including the trenches and holes;
covering said insulator with a layer of chemically vapor deposited silicon oxide using the TEOS with ozone pyrolytic process wherein the TEOS with ozone silicon oxide layer will partially fill said surface irregularities not filled by said insulator layer;
anisotropically etching back said TEOS with ozone silicon oxide layer thereby leaving said TEOS with ozone layer only in said surface irregularities and retaining a positive angle;
depositing a second insulating layer over said layer structure with said TEOS with ozone layer;
covering said second insulating layer with at least one spin-on-glass layer to fill the valleys of said irregular structure and curing said spin-on-glass layer;
partially blanket anisotropically etching said spin-on-glass layer through its thickness to underlying second insulating layer at its highest points and leaving said spin-on-glass layer portions in said valleys, whereby said second insulating layer prevents etching of said patterned conductive layer;
and
depositing a top dielectric layer over said spin-on-glass layer to complete said planarization.

5 more elements

Dependencies are inferred from the claim text.