Memory integrated circuit with balanced resistance

A semiconductor integrated circuit comprising:

• at least one memory cell, said cell comprising
• a buried conductor;
• first and second gates positioned on opposite sides of said conductor;
• a first junction between said first gate and said buried conductor, said first gate controlling current flow from said first junction to said conductor;
• a second junction between said second gate and said buried conductor, said second gate controlling current flow from said second junction to said conductor.