Back to results
US 5,352,923 AGranted
Trench resistors for integrated circuits
AssigneeNorthern Telecom Limited
InventorsJohn M. Boyd, Joseph P. Ellul, Sing P. Tay
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeNorthern Telecom Limited
InventorsJohn M. Boyd, Joseph P. Ellul, Sing P. Tay
Estimating the term…
A method is provided for forming multi-valued linear resistors for an integrated circuit using a single mask level. A plurality of trenches are defined in a substrate. Each trench has contact regions of a specific lateral dimension and a narrower portion extending therebetween. Successive conformal layers of a first dielectric layer, a first conductive layer of high resistivity and a second conductive layer of lower resistivity are provided to fill the trench. The amount of the second conductive layer which fills the trench depends on the width of the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Advantageously when the first and second conductive layers are provided from layers of undoped and doped polysilicon respectively, the trench dimensions control the amount of dopant incorporated in each region of the trench. After annealing to diffuse dopant, the wider end contact regions are heavily doped to form contact regions, and the intermediate narrow portion of the trench is doped to a level dependent on the width of the trench, thereby forming a resistive element having a resistivity inversely dependent on the trench width. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes.
An integrated circuit having a plurality of resistors of different resistance values,
An integrated circuit including a plurality of resistively conductive elements, each comprising:
An integrated circuit having a plurality of resistors of different resistance values,
Dependencies are inferred from the claim text.