US 5,352,905 AGranted

Semiconductor surge suppressor

AssigneeShindengen Electric Manufacturing Co., Ltd.

InventorKoichi Ohta

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Abstract

A thyristor type surge suppressor includes a P-type semiconductor substrate, an N-type first semiconductor layer provided in one surface of the semiconductor substrate, an N-type second semiconductor layer provided in the other surface of the semiconductor substrate, a P-type third semiconductor layer formed in the N-type first semiconductor layer so as to provide a plurality of first exposed regions of the N-type first semiconductor layer, a P-type fourth first semiconductor layer formed in the N-type second semiconductor layer so as to provide a plurality of second exposed regions of the N-type second semiconductor layer, a first electrode provided over the P-type third semiconductor layer and the of N-type first exposed regions, and a second electrode provided over the P-type fourth semiconductor layer and the N-type second exposed regions. In such a structure, the N-type first and second exposed regions are disposed so as to be opposed to the P-type fourth semiconductor layer and the P-type third semiconductor layer, respectively.

Claims16

Dependent claims

A two-terminal semiconductor surge suppressor comprising:

a semiconductor substrate of a first conductivity type having first and second surface portions opposed to each other;
a first semiconductor layer of a second conductivity type in the first surface portion;
a second semiconductor layer of the second conductivity type in the second surface portion;
a third semiconductor layer of the first conductivity type, in the first semiconductor layer, defining a plurality of first exposed regions of the first semiconductor layer;
a fourth semiconductor layer of the first conductivity type, in the second semiconductor layer, defining a plurality of second exposed regions of the second semiconductor layer, the plurality of the first exposed regions being opposed to the fourth semiconductor layer, and the plurality of second exposed regions being opposed to the third semiconductor layer;
a first electrode over the third semiconductor layer and the plurality of first exposed regions;
and
a second electrode over the fourth semiconductor layer and the plurality of second exposed regions,
wherein a distance D between each of the plurality of first exposed regions and one of the plurality of second exposed regions adjacent thereto, a dimension d of each of the plurality of the first and second exposed regions, and a distance Wp between the first and second semiconductor layers satisfy relationships of
Wp/2.ltoreq.D.ltoreq.2Wp and Wp.ltoreq.d.ltoreq.4Wp.

7 more elements

A three-terminal semiconductor surge suppressor comprising:

a semiconductor substrate of a first conductivity type having a first surface portion having first and second area, and a second surface portion opposed to the first surface portion;
a first semiconductor layer of a second conductivity type in the first area of the first surface portion;
a second semiconductor layer of the second conductivity type in the second area of the first surface portion;
a third semiconductor layer of the second conductivity type in the second surface portion, the third semiconductor layer being opposed to the first and second semiconductor layers;
a fourth semiconductor layer of the first conductivity type, in the first semiconductor layer, defining a plurality of first exposed regions of the first semiconductor layer;
a fifth semiconductor layer of the first semiconductor type, in the second semiconductor layer, defining a plurality of second exposed regions of the second semiconductor layer;
a sixth semiconductor layer of the first conductivity type formed in the third semiconductor layer so as to provide a plurality of third exposed regions of the third semiconductor layer, the plurality of the first and second exposed regions being opposed to the sixth semiconductor layer, and the plurality of third exposed regions being opposed to the fourth and fifth semiconductor layers;
a first electrode over the fourth semiconductor layer and the plurality of first exposed regions;
a second electrode over the fifth semiconductor layer and the plurality of second exposed regions;
and
a third electrode over the sixth semiconductor layer and the plurality of third exposed regions,
wherein a distance D between each of the plurality of first and second exposed regions and one of the plurality of third exposed regions adjacent thereto, a dimension d of each of the plurality of the first, second and third exposed regions, and a distance Wp between the first and second semiconductor layers and the third semiconductor layer satisfy relationships of
Wp/2.ltoreq.D.ltoreq.2Wp and Wp.ltoreq.d.ltoreq.4Wp.

10 more elements

Dependencies are inferred from the claim text.