Method of making semiconductor device with memory cells and peripheral transistors
AssigneeHitachi, Ltd.
InventorsKazuhiro Komori, Kenichi Kuroda, June Sugiura
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Abstract
Disclosed is a semiconductor integrated circuit device which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells, and which is used as EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.
Claims14
A method of manufacturing a semiconductor device, said semiconductor device comprising a first MISFET for a memory cell and a second MISFET for a peripheral circuit, said method comprising the steps of:
- providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, floating and control gate electrodes of said first MISFET being provided over said memory cell forming region, said control gate electrode being positioned over said floating gate electrode, and a first gate electrode of said second MISFET being provided over said peripheral circuit forming region;
- introducing a first impurity into said memory cell forming region, in self-alignment with both end portions of said floating gate electrode, for forming first regions of a first conductivity type;
- introducing a second impurity into said peripheral circuit forming region, in self-alignment with both end portions of said first gate electrode, for forming second regions of said first conductivity type, wherein an impurity concentration of said first regions is higher than that of said second regions;
- after the steps of introducing first and second impurities, forming first side wall spacers on both side surfaces of said control and floating gate electrodes, in self-alignment with said control and floating gate electrodes, and second side wall spacers on both side surfaces of said first gate electrode, in self-alignment with said first gate electrode;
- and
- introducing a third impurity into both said memory cell forming region and said peripheral circuit forming region, in self-alignment with said first and second side wall spacers, for forming third regions of said first conductivity type in said memory cell forming region and fourth regions of said first conductivity type in said peripheral circuit forming region, wherein an impurity concentration of said third regions is higher than that of said first regions, and wherein an impurity concentration of said fourth regions is higher than that of said second regions.
A method of manufacturing a semiconductor device, said semiconductor device comprising a first MISFET for a memory cell and a second MISFET for a peripheral circuit, said method comprising the steps of:
- providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, floating and control gate electrodes of said first MISFET being provided over said memory forming region, said control gate electrode being positioned over said floating gate electrode, and a first gate electrode of said second MISFET being provided over said peripheral circuit forming region;
- introducing a first impurity into said memory cell forming region, in self-alignment with both end portions of said floating gate electrode, for forming first regions of n-type conductivity;
- introducing a second impurity into said peripheral circuit forming region, in self-alignment with both end portions of said first gate electrode, for forming second regions of said n-type conductivity, wherein an impurity concentration of said first regions is higher than that of said second regions;
- after the steps of introducing first and second impurities, forming first side wall spacers on both side surfaces of said control and floating gate electrodes, in self-alignment with said control and floating gate electrodes, and second side wall spacers on both side surfaces of said first gate electrode, in self-alignment with said first gate electrode;
- and
- introducing a third impurity into said peripheral circuit forming region, in self-alignment with said second side wall spacers, for forming third regions of said n-type conductivity, an impurity concentration of said third regions being higher than that of said second regions.
Dependencies are inferred from the claim text.