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US 5,350,942 AGranted
Low resistance silicided substrate contact
AssigneeNational Semiconductor Corporation
InventorsRick C. Jerome, Frank Marazita
Life of this patent
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Abstract
Low resistance contacts for establishing an electrical pathway to an integrated surface substrate are provided. The pathway is formed by the connection of a p+ doped channel stop region with a p+ doped extrinsic layer. P+ doped polysilicon contacts are positioned on the substrate surface. In one embodiment, a metal silicide layer connects the polysilicon contacts and overlies the p+ doped extrinsic layer.
Claims4
In an integrated circuit a substrate contact comprising:
- a p+ doped channel stop region formed in a substrate and spaced apart from a top surface of said substrate;
- a p+ doped extrinsic region located within the substrate adjacent a top surface of said substrate and contacting said channel stop region;
- a first p+ doped polysilicon region formed on the top surface of said substrate adjacent said p+ doped extrinsic region;
- a second p+ doped polysilicon region formed on the top surface of said substrate adjacent said first p+ doped extrinsic region, and spaced from said first p+ doped polysilicon region;
- an oxide layer formed on the top surface of the substrate and spanning a distance between said first and said second p+ doped polysilicon regions;
- and
- said p+ doped extrinsic region including an extended region located under said oxide layer and extending deeper into said channel stop region than a remaining portion of said p+ doped extrinsic region.
4 more elements
Dependencies are inferred from the claim text.