Method of manufacturing a semiconductor IC device having multilayer interconnection structure

A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

• forming a first insulating layer on a major surface of a semiconductor substrate;
• forming a first-level metal wiring layer on the first insulating layer
• forming a second insulating layer on the first insulating layer and the first-level metal wiring layer;
• coating the second insulating layer with a photoresist, and removing that part of the photoresist which is coated on a region of the first-level metal wiring layer containing a contact formation region;
• exposing part of the first-level metal wiring layer by removing at least that part of the second insulating layer which is located on the side portion of the first-level metal wiring layer in the vicinity of the contact formation region;
• increasing the width of the contact formation region of the first-level metal wiring layer by forming a metal layer on the exposed surface of the first-level metal wiring layer;
• forming a third insulating layer on the second insulating layer, the first-level metal wiring layer, and the metal layer;
• forming, by anisotropic etching, a through hole in that portion of the third insulating layer which is located on the contact formation region of the first-level metal wiring layer;
• and
• forming a second-level metal wiring layer such that it fills the through hole, extends on part of the third insulating layer, and is electrically connected to the first-level metal wiring layer.