CMOS memory cell array
AssigneeTexas Instruments Incorporated
InventorsDave J. McElroy, Manzur Gill, Pradeep L. Shah
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Abstract
A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silicon dopant is implanted in areas not covered by the source line pattern to form buried n+ source lines. The field oxide regions are formed in areas not covered by the moat pattern. Subsequent fabrication steps may be in accordance with conventional CMOS fabrication techniques.
Claims7
A method of fabricating rows and columns of CMOS memory cells in an array on a semiconductor substrate having a first conductivity type, said array having source lines parallel to said rows of cells, comprising the steps of:
- forming a column-photoresist pattern on the semiconductor surface to define field oxide isolation regions between areas where said columns of cells are to be formed;
- implanting a dopant of said first conductivity-type in areas not covered by said column-photoresist pattern to form a channel stop region;
- removing said column-photoresist pattern;
- forming a row-photoresist pattern on the semiconductor surface to define said source lines for connecting the sources of rows of said cells to be formed;
- implanting said source lines with a dopant of a second conductivity-type opposite said first conductivity-type along areas not covered by said row-photoresist pattern;
- removing said row-photoresist pattern;
- and then
- growing an oxide layer for isolation in said field oxide isolation regions.
Dependencies are inferred from the claim text.