Programmable logic device having security elements located amongst configuration bit location to prevent unauthorized reading

A method for improving design security in a programmable logic device on an integrated circuit die, comprising:

• providing on the integrated circuit die a plurality of programmable security elements, each having a state which allows readback and a state which does not allow readback;
• disposing each of the programmable security elements in proximity to areas containing data for the programmable logic device on the integrated circuit die at irregular locations in the programmable logic device;
• connecting said plurality of programmable security elements to the integrated circuit, wherein said plurality of programmable security elements enables said data to be read out from the programmable logic device only when each of said plurality of programmable security elements is set to its state which allows readback;
• and said plurality of programmable security elements disables the reading of said data when at least one of said programmable security elements is set to its state which does not allow readback;
• and
• setting at least one of said programmable security elements to its state which does not allow readback.

A programmable logic device comprising:

• an array of programmable configuration elements;
• a plurality of programmable security elements, each having a first state and a second state, each programmable security element being distributed among elements of said array of programmable configuration elements;
• said plurality of programmable security elements enabling data to be read from the programmable logic device only when each of said plurality of programmable security elements is et to the first state;
• and
• said plurality of programmable security elements disabling the reading of data when at least one of said programmable security elements is set to the second state.

An EPROM-based programmable logic device comprising:

• at least one EPROM array for storing user-defined data;
• a plurality of programmable security bits distributed among programmable elements of said EPROM array;
• said plurality of programmable security bits enabling data to be read from the EPROM array when each of the plurality of programmable security bits is set to one of its binary values;
• and
• said plurality of programmable security bits disabling the reading of configuration data when at least one of said programmable security bits is set to the other of its binary values.

A programmable logic device comprising:

• a plurality of programmable security elements, each having a first state and a second state;
• an array of programmable configuration elements, wherein said plurality of programmable security elements are distributed in an irregular pattern on said array;
• said plurality of programmable security elements enabling data to be read from the programmable logic device only when each of said plurality of programmable security elements is set to the first state;
• and
• said plurality of programmable security elements disabling the reading of data when at least one of said programmable security elements is set to oZ