Semiconductor input protective device against external surge voltage

A semiconductor input protective device formed between a power source line and a ground line and connected to an internal circuit, said device comprising:

• an NPN type bipolar transistor having a collector connected to a signal line extending to a pad, and an emitter and a base commonly connected to a ground line;
• a first N-channel MIS transistor in which one of a drain and a source thereof is connected to said signal line and the other one of the drain and the source is connected to said power source line, said first N-channel MIS transistor having a threshold voltage higher than a power source voltage supplied to said power source line and having a gate insulation film thicker than a gate insulation film of a MIS transistor constituting said internal circuit;
• and
• a second N-channel MIS transistor connected in parallel with said first N-channel MIS transistor, with a gate of one of said first and second N-channel MIS transistors being connected to the signal line and a gate of the other one of said first and second N-channel MIS transistors being connected to the power source line.