Flash memory cell and its operation
AssigneeUnited Microelectronics Corp.
InventorGary Hong
Life of this patent
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Abstract
A method of operating a flash memory semiconductor device is provided. The semiconductor device formed on a substrate lightly is doped with a dopant. A source region and a drain region are formed in the substrate on the surface thereof. A dielectric layer is deposited upon the substrate. A floating gate electrode is formed on the dielectric layer proximate to at least the edges of the source region and the drain region. Additional dielectric material is deposited upon the surface of the floating gate electrode, and a gate electrode is deposited upon the surface of the additional dielectric material.
Claims18
A split gate semiconductor device formed on a substrate lightly doped with a dopant, comprising
- a source region and a drain region in said substrate on the surface thereof,
- a dielectric layer deposited upon said substrate, a floating gate electrode formed on said dielectric layer proximate to at least the edge of said drain region with said source region spaced away from said floating gate structure while in proximity thereto in accordance with a split gate arrangement,
- additional dielectric material deposited upon the surface of said floating gate electrode, and a control gate electrode deposited upon the surface of said additional dielectric material, and
- high voltage generator means for applying a programming voltage to said control gate electrode,
- means for providing programming of said device with said drain region at a relatively low voltage, said source region at an intermediate positive voltage, said control gate electrode at a relatively high voltage, and said substrate at a relatively negative voltage.
A split gate semiconductor device formed on a substrate lightly doped with a dopant, comprising
- a source region and a drain region in said substrate on the surface thereof,
- a dielectric layer deposited upon said substrate, a floating gate electrode formed on said dielectric layer proximate to at least the edge of said drain region with said source region spaced away from said floating gate structure while in proximity thereto in accordance with a split gate arrangement,
- additional dielectric material deposited upon the surface of said floating gate electrode, and a control gate electrode deposited upon the surface of said additional dielectric material, and
- high voltage generator means for applying a programming voltage to said control gate electrode,
- means for erasing data in said device by applying a voltage ranging from a neutral voltage to a positive voltage to said drain region, applying a floating voltage to said source, applying a negative voltage to said control gate and applying a neutral voltage to said substrate.
A method of operating a split gate, flash memory cell device,
- said device including a semiconductor substrate, a source region, a drain region, a dielectric layer deposited upon said substrate, and a floating gate electrode formed on said dielectric layer proximate to at least the edge of said drain region with said source region spaced away from said floating gate structure while in proximity thereto in accordance with a split gate arrangement,
- said device including additional dielectric material deposited upon the surface of said floating gate electrode, and
- a control gate electrode deposited upon the surface of said additional dielectric material,
- the improvement comprising the step of applying a high programming voltage to said control gate electrode during programming, and providing programming of said device with the drain region at a relatively low voltage, said source region at an intermediate positive voltage, said control gate at a relatively high voltage, and said substrate at a relatively negative voltage.
A semiconductor flash memory device formed on a substrate lightly doped with a dopant,
- a source region and a drain region in said substrate on the surface thereof,
- a dielectric layer deposited upon said substrate, a floating gate electrode formed on said dielectric layer proximate to at least the edge said drain region with said source region spaced away from said floating gate structure in a split gate arrangement,
- additional dielectric material formed upon the surface of said floating gate electrode, and a control gate electrode deposited upon the surface of said additional dielectric material, and
- high voltage generator means for applying a programming voltage to said control gate electrode, wherein the voltages applied to elements of said device for programming, erasure and reading are substantially within the ranges as follows:
- ______________________________________ Drain Source Control gate Substrate ______________________________________ Program 0 V 3.about.5 V 12.about.14 V -3.about.-5 V Erase 0.about.5 V Floating .about.-10 V 0 V Read .about.1 V 0 V 3.about.5 V 0 V ______________________________________
Dependencies are inferred from the claim text.