Semiconductor chip test jig
AssigneeDigital Equipment International Limited
InventorsRoss L. Armstrong, George A. Meiklejohn
Life of this patent
Estimating the term…
Abstract
A semiconductor chip test jig for testing a chip 10 with "gull-wing" leads 11 comprises a body 20 and a cover 30. The body 20 has sets of fins or combs 23 which engage with the leads 11 to locate the chip 10 in the horizontal plane; the cover 30 has a set of "knife-edge" lead supports 35 formed to match a trim and form jig in the region of the leads 11 from where they emerge from the encapsulation of the chip 10 to their first bends; and the body 20 has a set of spring-loaded pins 24 which contact the leads opposite the lead supports.
Claims12
A test jig for leaded semi-conductors comprising:
- a body including a bottom and side walls, said side walls extending laterally away from said bottom to form a well space region therebetween for housing a leaded semiconductor during testing;
- the bottom having openings extending therethrough;
- resiliently biased contact pins extending through the openings for supporting contact with the leads of said semiconductor;
- fins located in the well space region extending inwardly of two opposing side walls towards a central region of said well for locating leads of said semi-conductor in alignment with said contact pins for support on the the ends thereof;
- said leads of said semiconductor being placed between said fins;
- and
- a cover comprising holding surfaces positioned to contact said leads at directly opposite locations on said leads when said body and and cover are brought together.
A test jig for leaded semi-conductor comprising:
- a body including a bottom and side walls, said side walls extending laterally away from said bottom to form a well space region therebetween for housing a leaded semiconductor during testing;
- the bottom having openings extending therethrough;
- resiliently biased contact pins extending through the openings for supporting contact with the leads of said semiconductor;
- fins located in the well space region;
- adjacent fins forming a guide space therebetween;
- the guide spaces being positioned for alignment receipt of the leads of the semiconductor placed in the well space region of the jig for testing;
- and
- a cover comprising holding surfaces positioned to contact said leads at directly opposite locations on said leads when said body and and cover are brought together.
Dependencies are inferred from the claim text.