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US 5,347,185 AGranted
Protection structure against latch-up in a CMOS circuit
AssigneeSGS-Thomson Microelectronics S.A.
InventorFrancois Tailliet
Life of this patent
Estimating the term…
Abstract
A CMOS circuit protected against latch-up. A limiter parallel to the internal circuitry of the CMOS circuit increases the external current for the triggering of the latch-up in the event of overvoltage on the supply. In one embodiment, the parallel limiter is intrinsically protected against electrostatic discharges. In another embodiment, the limiter is protected by a series connected resistor and a separate shunt-connected ESD protection structure.
Claims24
A CMOS circuit protected against latch-up, comprising:
- internal circuitry connected between a first more positive supply terminal and a second more negative supply terminal to draw power therefrom, said internal circuitry having, as known parameters, a current I.sub.1 and a voltage V.sub.1 for the triggering of the latch-up phenomenon;
- a limiter, connected, in parallel with the internal circuitry, between the first supply terminal and the second supply terminal, this limiter having a triggering threshold below voltage V.sub.1 and consuming current of a value far higher than I.sub.1 when a voltage of V.sub.1 or greater is applied between the first and second supply terminals.
A CMOS integrated circuit, comprising:
- first and second power supply input connections;
- a plurality of active devices connected to implement a desired circuit configuration, and operatively connected to be powered from said first and second power supply input connections, and configured to reliably withstand peak voltages of at least a specified value Vmax;
- a limiter circuit, having a nonlinear response with a low dynamic impedance R.sub.e at applied voltages greater than a threshold voltage E;
- said limiter being connected, in series with a resistance, between said first and second power supply connections;
- an electrostatic discharge protection device, connected directly between said first and second power supply connections, said electrostatic discharge protection device having a nonlinear response with a very low impedance at applied voltages greater than a threshold voltage Vo;
- wherein said limiter and said electrostatic discharge protection device have respective device parameters such that Vmax<E<Vo.
3 more elements
A CMOS integrated circuit, comprising:
- first and second power supply input connections;
- a plurality of active devices connected to implement a desired circuit configuration, and operatively connected to be powered from said first and second power supply input connections, and configured to reliably withstand peak voltages of at least a specified value Vmax;
- said plurality of active devices collectively having a latchup trigger voltage of least V1, and a latchup holding current of at least I1;
- a limiter circuit, comprising a Zener diode structure having a threshold voltage E;
- said limiter being connected, in series with a resistance, between said first and second power supply connections;
- an electrostatic discharge protection device, comprising a diode-connected bipolar transistor connected directly between said first and second power supply connections, said electrostatic discharge protection device having a threshold voltage Vo;
- wherein said limiter and said electrostatic discharge protection device have respective device parameters such that Vmax<E, E<V1, and E<Vo.
4 more elements
Dependencies are inferred from the claim text.