Stacked CMOS latch with cross-coupled capacitors
AssigneeTexas Instruments Incorporated
InventorRavishankar Sundaresan
Life of this patent
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Abstract
A latch (80) utilizing stacked MOS technology is provided. Latch (80) is formed generally in relation to a semiconductor substrate (82). An N channel transistor is provided with first and second diffused regions (96 98) and a gate conductor (86) . A P channel transistor is provided with first and second doped regions (106, 110) having a channel region (108) therebetween. The second diffused region (98) of the N channel transistor also functions as the gate conductor for the P channel transistor. A capacitive element exists by having an insulating layer (84) or layers (84, 100) between first doped region (104) and second diffused region (98).
Claims10
A SRAM comprising:
- a bulk transisitor having a gate;
- a stacked transistor having a gate and first and second source/drain regions;
- and
- a discrete first capacitor plate located between said gate of said bulk transistor and said first source/drain region of said stacked transistor;
- wherein said gate of said stacked transistor comprises a first diffused region, said first diffused region also forming a first source/drain region of said bulk transistor and a second capacitor plate.
Dependencies are inferred from the claim text.