US 5,347,151 AGranted

DRAM with memory cells having access transistor formed on solid phase epitaxial single crystalline layer and manufacturing method thereof

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsMasahiro Shimizu, Takehisa Yamaguchi, Natsuo Ajika

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Abstract

Access transistors of memory cells in a DRAM are formed in a solid phrase epitaxial single crystalline layer on the surface of a silicon substrate. A bit line extending over the surface of an element isolation and insulation film is formed by patterning a polycrystalline silicon layer extending to the single crystalline silicon layer as a layer. A stacked capacitor is connected to one source/drain of the access transistor through a conductive layer extending to the single crystalline silicon layer and over a field oxide film. Part of the stacked capacitor extends over the bit line. The connection region of the bit line, the capacitor and the source/drain is formed above the element isolation and insulation film, so that the source/drain region of the access transistor can be reduced.

Claims7

Dependent claims

A DRAM with memory cells each having one transistor and one capacitor, comprising:

a silicon substrate of a first conductivity type having a main surface;
a single crystalline silicon layer having an upper surface and a lower surface, said lower surface being in contact with the main surface of said silicon substrate, said single crystalline silicon layer being an epitaxial single crystal layer grown in contact with the main surface of the silicon substrate;
a transistor having first and second impurity regions of a second conductivity type spaced apart from each other on the upper surface of said single crystalline silicon layer, a gate insulating film on the surface of said single crystalline silicon layer, and a gate electrode on the gate insulating film between the first and second impurity regions;
a capacitor having a first electrode layer connected to said first impurity region of said transistor, a dielectric layer formed on the surface of said first electrode layer and a second electrode layer formed on the surface of said dielectric layer;
a first conductive layer in contact with said gate electrode;
and
a bit line comprising a second conductive layer of polycrystalline silicon formed as a common layer as said single crystalline silicon layer and being in contact with said second impurity region of said transistor.

4 more elements

Dependencies are inferred from the claim text.