Process for forming a trench capacitor memory cell

A process for forming a trench capacitor memory cell, comprising the steps of:

• a) forming a pad oxide layer, a first silicon nitride layer and a first oxide layer upon a silicon substrate, patterning to form an active region by etching the pad oxide layer, the first silicon nitride layer and the first oxide layer so that the remaining portions define the active region, and forming a field region by etching the silicon substrate except for the active region;
• b) depositing a second silicon nitride layer to a certain thickness, depositing a second oxide layer thereupon, and forming an active region insulating layer around the active region by anisotropic dry etching the second oxide layer and the second nitride layer so that the insulating layer comprising nitride and oxide remains on the sides and top of the active region;
• c) growing a third oxide layer on the bottom of the field region by a thermal oxidation process;
• d) depositing a doped first polysilicon, and forming a polysilicon plug within the field region by anisotropic dry etching the first polysilicon;
• e) depositing a fourth oxide layer, defining a trench region within the field region by a photoresist process, dry-etching the fourth oxide layer using the photoresist as a mask, sequentially etching the first polysilicon and the third oxide layer, wherein the photoresist used as a mask substantially remains, and forming a trench by anisotropic dry etching the silicon substrate;
• f) removing the photoresist, removing the exposed portions of the first and second oxide layers and the fourth oxide layer by an oxide layer etching process, and forming a fifth oxide layer on the inside walls of the trench and around the polysilicon plug by a thermal oxidation process;
• g) etching the exposed portion of the first and second silicon nitride layers, depositing a doped second polysilicon, forming a flat insulating layer, and forming an insulating plug within the trench by an etching process;
• h) patterning a capacitor storage electrode in a self-aligned manner by etching back the exposed second polysilicon, removing the insulating plug from within the trench, and forming a capacitor dielectric layer and capacitor plate electrode, thereby forming a capacitor;
• and
• i) forming a transistor gate, and forming a source/drain region of the transistor in a self-aligned manner.