Method for fabricating semiconductor memory device

A method for fabricating a semiconductor memory device comprising the steps of:

• forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source, drain and gate electrode is formed;
• forming a first contact hole by partly removing said first insulating layer formed on said drain region, said first contact hole removing step including the steps of:
• forming a first material layer where a first pattern for forming said first contact hole is formed, on the overall resultant structure where said first insulating layer is formed,
• forming a third spacer on the inner side walls of said first pattern, and
• anisotropically etching on the resultant structure using said first pattern and third spacer as an etching mask and taking the surface of said substrate as its etching end point;
• forming a bit line connected to said drain region via said first contact hole;
• forming a second planarized insulating layer on the overall resultant structure;
• forming a second contact hole by partly removing said first and second insulating layers formed on said source region, said second hole forming step including the steps of:
• forming a second material layer where a second pattern for forming said second contact hole is formed on the overall resultant structure where said second insulating layer is formed,
• forming a fourth spacer on the inner side wall of said second pattern, and
• anisotropically etching on the resultant structure using said second pattern and fourth spacer as an etching mask and taking the surface of said substrate as its etching end point;
• and
• forming a storage electrode connected to said source region via said second contact hole.