US 5,345,417 AGranted

EPROM device with metallic source connections and fabrication thereof

AssigneeSGS-Thomson Microelectronics S.A.

InventorPier L. Crotti

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Abstract

An integrated EPROM device which can be manufactured using standard high-definition photolithographic techniques with unit cells of markedly reduced dimensions as compared to the minimum dimensions that can be achieved with the prior art, has field isolation structures between adjacent cells along rows of the array in the form of continuous isolation strips which extend for the whole column length of the array, thus avoiding the problems associated with photolithographic defining rectangular geometries. The electrical interconnection between the sources of the cells of each row is achieved by a special metal source "line" formed between two adjacent gate lines, using for the purpose a conformally deposited metal layer from which both the drain contacts and these source interconnection metal "lines" are created in a self-alignment way.

Claims7

Dependent claims

An integrated EPROM device comprising an array of unitary memory cells arranged in rows and columns, each cell having a gate structure comprising a floating gate and a control gate, insulated therefrom and superimposed over the floating gate, between a source area or source region and a drain area or drain region of a semiconductor substrate, the control gate of the cells of each row being connected in common through a respective gate line, each common drain of two adjacent cells belonging to the same column being connected through a contact to a drain line connecting in common the drains of all the cells of the column, means for connecting in common the source of all the cells disposed on the same row, a field dielectric structure separating the cells disposed along the same row, wherein

said field dielectric structure is in the form of continuous parallel strips that extend uninterrupted for the whole column length of said array;
said means for connecting the source of all the cells disposed along the same row are in the form of continuous parallel strips of a conductive material, running in a row-wise direction, between two of said gate lines and laying over, and in contact with, said source areas of the semiconductor substrate and over said parallel uninterrupted strips of field dielectric at intersections therewith.

An electrically programmable floating gate memory array, comprising:

a plurality of parallel, uninterrupted strips of field oxide in a surface of a semiconductor substrate, wherein the strips define exposed substrate surface strips oriented in a first direction;
a plurality of control gates formed from parallel strips of a conductive material, wherein the control gates are oriented in a second direction orthogonal to the first direction, wherein the control gates further have floating gates beneath each control gate wherever it crosses an exposed substrate surface strip, and wherein the control gates define a plurality of alternating source and drain regions in the exposed substrate surface strips on either side of the floating gates;
a plurality of continuous metal conductive strips oriented in the second direction, wherein the continuous metal conductive strips are located between alternating pairs of control gates and make contact to source regions lying therebeneath in the substrate, whereby all source regions between a pair of control gates are electrically connected together only through a continuous metal conductive strip;
a plurality of conductive metal pillars located above each drain region, wherein metal pillars in drain regions separated only by a portion of a field oxide strip are not in electrical contact;
an insulating layer overlying the control gates, continuous metal conductive strips, and conductive metal pillars, wherein the insulating layer has an opening therethrough above each of the conductive metal pillars to expose the pillars;
and
a plurality of metal bit lines oriented in the first direction, each bit line contacting only every conductive metal pillar located between a pair of field oxide strips.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/016,741Filed 11 Feb 1993 · division
Priority: IT 83651 A/8922 Dec 1989
Granted: 6 Sep 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

H10B 41/00
Electrically erasable-and-programmable rom [eeprom] devices comprising floating gates
H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10B
Electronic memory devices

Family

Serial632,101Parent of this division · filed 20 Dec 1990
US 5,210,046 AParent of this division
US 5,345,417 AThis patent

From the US filing history. Foreign family members aren’t listed.

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