Semiconductor memory device having ferroelectric film

A nonvolatile semiconductor memory device, comprising:

• a semiconductor substrate;
• a plurality of memory cells aligned in rows and columns in a matrix array on said semiconductor substrate, each memory cell including:
• a storing field effect transistor having a ferroelectric gate film formed on said semiconductor substrate,
• a gate electrode formed on the ferroelectric gate film,
• a reading transistor connected in series to said storing field effect transistor, and
• a writing and erasing transistor connected to the gate electrode of said storing field effect transistor;
• a separate corresponding reading word line for each row of said rows, each reading word line connected to a gate of said reading transistor in each memory cell of the memory cells aligned in the row to which the reading word line corresponds;
• a separate corresponding writing and erasing word line for each row of said rows, each writing and erasing word line connected to said writing and erasing transistor at a side of said writing and erasing transistor opposite to said storing field effect transistor in each memory cell of the memory cells aligned in the row to which the writing and erasing word line corresponds;
• a separate corresponding bit line for each column of said columns, each bit line connected to said reading transistor at a side of said reading transistor opposite to said storing field effect transistor in each memory cell of the memory cells aligned in said each column;
• means for applying a voltage provided on any one of said bit lines, to a gate of said writing and erasing transistor of each of the memory cells aligned in the column to which the one bit line corresponds;
• writing means for selecting any first selected memory cell from among the memory cells of the matrix array and writing data in the first selected memory cell, said writing means including:
• means for applying a first specified voltage to the bit line connected to the first selected memory cell to make the writing and erasing transistor thereof conductive, and
• writing voltage applying means for applying a writing voltage to the writing and erasing word line connected to the first selected memory cell to invert a direction of a polarization of said ferroelectric gate film or retain the polarization in an initial direction, in accordance with data to be written;
• reading means for selecting any second selected memory cell from among the memory cells of the matrix array and reading data from the second selected memory cell, said reading means including:
• means for applying a second specified voltage to the reading word line connected to the second selected memory cell to make the reading transistor thereof conductive, and
• data detecting means for checking whether a series circuit of said reading transistor and said storing field effect transistor of the second selected memory cell is conductive or not;
• and
• erasing means for selecting any third selected memory cell from among the memory cells of the matrix array and erasing data from the third selected memory cell, said erasing means including:
• means for applying a third specified voltage to the bit line connected to the third selected memory cell to make the writing and erasing transistor thereof conductive, and
• means for applying an erasing electric field to the ferroelectric gate film contained in the storing field effect transistor of the third selected memory cell to turn the polarization of said ferroelectric gate film to a specified direction.

A method of driving a nonvolatile semiconductor memory device which includes memory cells disposed in rows and columns of a matrix array on a semiconductor substrate, each memory cell of the matrix array including a storing field effect transistor having a ferroelectric gate film formed on the semiconductor substrate and a gate electrode formed on the ferroelectric gate film, a reading transistor connected in series to said storing field effect transistor, and a writing and erasing transistor connected to the gate electrode of said storing field effect transistor;

• a separate corresponding reading word line for each row of said rows, each reading word line connected to a gate of said reading transistor in each of the memory cells aligned in said each row;
• a separate corresponding writing and erasing word line for each row of said rows, each writing and erasing word line connected to said writing and erasing transistor at a side of said writing and erasing transistor opposite to said storing field effect transistor in each of the memory cells aligned in said each row;
• a separate corresponding bit line for each column of said columns, each bit line connected to said reading transistor at a side of said reading transistor opposite to said storing field effect transistor in each of the memory cells aligned in said each column;
• and
• means for applying a voltage provided on any one of said bit lines, to a gate of said writing and erasing transistor of each of the memory cells aligned in the column to which the one bit line corresponds;
• said method comprising the steps of:
• in selecting any memory cell and writing data in the selected memory cell, applying a writing voltage to said writing and erasing word line connected to the selected memory cell to invert a direction of a polarization of said ferroelectric gate film or retain the polarization in an initial direction in accordance with data to be written, and further applying a first specified voltage to said bit line connected to the selected memory cell to make said writing and erasing transistor conductive;
• in selecting any memory cell and reading data from the memory cell, applying a second specified voltage to said reading word line connected to the selected memory cell to make said reading transistor conductive, and checking whether a series circuit of said reading transistor and said storing field effect transistor in the selected memory cell is conductive or not;
• and
• in selecting any memory cell and erasing data in the memory cell, applying a third specified voltage to said bit line connected to the selected memory cell to make said writing and erasing transistor conductive, and applying an erasing electric field to said ferroelectric gate film contained in said storing field effect transistor in the selected memory cell to turn the polarization thereof to a specified direction.

A method of driving a nonvolatile semiconductor memory device which includes memory cells disposed in rows and columns of a matrix array on a semiconductor substrate, each memory cell of the matrix array including a storing field effect transistor having a ferroelectric gate film formed on the semiconductor substrate and a gate electrode formed on the ferroelectric gate film, a reading transistor connected in series to the storing transistor, and a writing and erasing transistor connected to the gate electrode of the storing transistor;

• a separate corresponding reading word line for each row, each reading word line connected to a gate of the reading transistor in each memory cell aligned in the row to which the reading word line corresponds;
• a separate corresponding writing and erasing word line for row, each writing and erasing word line connected to the writing and erasing transistor at a side of the writing and erasing transistor opposite to the storing transistor in each memory cell aligned in the row to which the writing and erasing word line corresponds;
• a separate corresponding bit line for each column, each bit line connected to the reading transistor at a side of the reading transistor opposite to the storing transistor in each memory cell aligned in the column to which the bit line corresponds;
• and means for applying a voltage provided on any one of the bit lines to a gate of the writing and erasing transistor of each memory cell aligned in the column to which the one bit line corresponds, said method comprising the steps of:
• (a) selecting a memory cell from among the memory cells of the matrix array and reading data from the selected memory cell, including
• applying a first specified voltage to the reading word line connected to the selected memory cell to make the reading transistor thereof conductive, and
• checking whether a series circuit of the reading transistor and the storing transistor of the selected memory cell is conductive or not;
• (b) selecting a memory cell from among the memory cells of the matrix array, and erasing data in the selected memory cell, including
• applying a second specified voltage to the bit line connected to the selected memory cell to make the writing and erasing transistor thereof conductive, and
• applying an erasing electric field to the ferroelectric gate film contained in the storing transistor in the selected memory cell to turn the polarization thereof to a specified direction;
• and
• (c) after said step (b), selecting the memory cell selected in said step (b), and writing data in the selected memory cell, including
• further applying a third specified voltage to the bit line connected to the selected memory cell to make the writing and erasing transistor conductive, and
• applying a writing voltage to the writing and erasing word line connected to the selected memory cell to retain the polarization of the ferroelectric gate film in the specified direction or invert the direction of polarization, in accordance with the data to be written.