US 5,345,357 A · ESD protection of output buffers

Abstract

A particular electrostatic discharge (ESD) protection problem is faced when only n-channel output transistors are present, since there is no p-n junction that could serve to clamp positive ESD voltages, as would be the case if a p-channel output transistor were present. In the present technique, a capacitor couples a bond pad to the gate of a protective transistor that applies a turn-on voltage to the gate of an n-channel output transistor. In this manner, the output transistor itself is used to conduct the ESD current to a power supply conductor (V.sub.SS). In one embodiment, to assist in the turn-on of the n-channel output transistor, a transistor couples the bond pad to the n-tub in which the p-channel pre-driver transistor is formed. Conduction through this transistor raises the n-tub voltage when an ESD event occurs, thereby preventing the p-n junction of the p-channel driver transistor from clamping the turn-on voltage, which would limit the protection obtained by this technique. This technique is especially valuable for SCSI (Small Computer System Interface) chips, since only n-channel output transistors are used. It may also be used in TTL-output buffers, which also use n-channel pull-up and pull-down devices. P-channel output devices may be comparably protected.

Claims17

Dependent claims

An integrated circuit comprising an output transistor having:

a first controlled electrode coupled to a power supply conductor, a second controlled electrode coupled to an output conductor, and a control electrode coupled to receive an information signal;
characterized in that said integrated circuit further comprises a protective device having:
a first controlled electrode coupled to said output conductor, a second controlled electrode coupled to the control electrode of said output transistor, and a control electrode coupled to said output conductor so as to cause said output transistor to conduct during an electrostatic discharge;
wherein said protective device is a field effect transistor, and further comprising a capacitor connected between said output conductor and the gate of said protective transistor;
and still further comprising a resistor connected between the gate of said protective transistor and a power supply conductor, so that said protective transistor does not conduct in the absence of an electrostatic discharge event.

2 more elements

An integrated circuit comprising:

a field effect pull-up transistor of a given conductivity type having a source coupled to a positive power supply conductor, a drain coupled to an output conductor, and a gate coupled to receive an information signal;
and a field effect pull-down transistor of said given conductivity type having a source coupled to a negative power supply conductor, a drain coupled to said output conductor, and a gate coupled to receive said information signal;
characterized in that said integrated circuit further comprises first and second field effect protective transistors, both of said given conductivity type;
wherein the first protective transistor has a first source/drain electrode coupled to the gate of said pull-up transistor, a second source/drain electrode coupled to said output conductor, and a gate electrode;
and wherein the second protective transistor has a first source/drain electrode coupled to the gate of said pull-down transistor, a second source/drain electrode coupled to said output conductor, and a gate electrode;
and still further comprises means for coupling the gate electrodes of said first and second protective transistors to said output conductor so as to cause said pull-up and pull-down transistors to conduct during an electrostatic discharge event.

3 more elements

Dependencies are inferred from the claim text.

ESD protection of output buffers

Life of this patent

ESD protection of output buffers

Life of this patent

Abstract

Claims17