Semiconductor device for minimizing diffusion of conductivity enhancing impurities from one region of a polysilicon layer to another

An SRAM memory device comprising:

• a first transistor having a source coupled to ground, a drain and a gate;
• a second transistor having a source coupled to ground, a drain coupled to the gate of the first transistor, and a gate coupled to the drain of the first transistor;
• a third transistor having a source coupled to a first bit line, a drain connected to the drain of the first transistor, and a gate connected to a word line;
• a fourth transistor having a source coupled to a second bit line, a drain connected to the drain of the second transistor, and a gate connected to the word line;
• a first resistive element coupled between the drain of the first transistor and a power source;
• and
• a second resistive element coupled between the drain of the second transistor and the power source;
• the first and second resistive elements being formed in a polysilicon layer, the polysilicon layer comprising:
• two n-type regions separated by a p-type region, the polysilicon layer having interfaces between the p-type region and each of the n-type regions;
• and
• a diffusion barrier region disposed at each of the interfaces between the p-type region and the two n-type regions, the diffusion barrier regions having a selected width and containing a diffusion inhibiting at a selected concentration, the p-type region being substantially void of the diffusion inhibiting impurity.