US 5,256,274 A · Selective metal electrodeposition process

Abstract

A process and apparatus for advanced semiconductor applications which involves the selective electrodeposition of metal on a semiconductor wafer is described. The present invention has significant economic and performance advantages over the current state of the art. It addresses problems associated with cleanliness (a major issue with sub-micron processing) , metal thickness uniformity, step coverage and environmental concerns. A metal with better device performance capabilities compared to the standard aluminum is also employed. The hardware allows the selective deposition to occur without allowing the electrolyte to contact the rear of the wafer or the electrodes contacting the front wafer surface. A virtual anode improves the primary current distribution improving the thickness uniformity while allowing optimization of other film parameters with the remaining deposition variables. Using this process and the associated hardware, metal lines are selectively deposited with contacts or vias completely filled without the need for plasma etching the deposited metal.

Claims9

Dependent claims

A wafer level sub micron interconnect metallization process for electrodeposition of metal such as copper, silver or gold onto a semiconductor wafer having an active layer such as silicon, said process comprising the steps of

depositing an electrically conducting layer on said wafer having contacts and vias, to prevent metal diffusion to said silicon, and
to provide a sufficient adhesion surface for the electrodeposited metal,
placing, using an inert photoresist metal mask process, a first metal mask layer onto said wafer,
selectively depositing said metal onto said conducting layer of said semiconducting wafer to form one or more lines,
removing said first metal mask layer from said wafer, and
electrochemically etching to increase a radius of curvature of edges of said lines, thereby facilitating planarization and decreasing line-to-line capacitance.

3 more elements

providing a semiconductor wafer with active device semiconductor,
depositing, using a diffusion barrier deposition process, an electrically conducting layer on said wafer to provide adequate adhesion to said wafer, to provide ohmic contact to said wafer and to prevent metal diffusion to said active device semiconductor or other semiconductor areas of said wafer,
depositing, using an electrically conducting nucleation layer deposition process, an ohmic contact to diffusion barrier layer which provides a sufficient adhesion surface and nucleation surface for the electrodeposited metal,
placing a non-conducting mask onto said diffusion barrier/nucleation layer on said semiconductor wafer,
selectively depositing said metal onto said diffusion barrier/nucleation layer on said semiconductor wafer to form one or more lines having corners and edges,
removing the non-conducting mask while not adversely affecting the electrodeposited metal, and
electrochemically etching to increase a radius of curvature of the corners and edges of metal lines to simplify planarization processing and decrease line to line capacitance.

4 more elements

Dependencies are inferred from the claim text.

Selective metal electrodeposition process

Life of this patent

Selective metal electrodeposition process

Life of this patent

Abstract

Claims9