Method of manufacturing a floating gate type nonvolatile memory cell having an offset region

A method of manufacturing a floating gate type nonvolatile memory cell having an offset region, comprising the steps of:

• forming a first insulating film on a substrate of a first conductivity type;
• forming a first gate electrode on said first insulating film;
• forming a second insulating film on said first gate electrode;
• forming an injection blocking film, for blocking impurity injection, so as to cover said first gate electrode;
• removing a portion of said injection blocking film by anisotropic etching, such that said injection blocking film remains only on the side wall of said first gate electrode and a portion of said substrate adjacent thereto, a lateral extent of said blocking film defining an offset region;
• injecting an impurity of a second conductivity type into said substrate, using said first gate electrode and the remaining portion of said injection blocking film as a mask;
• removing the remaining portion of said injection blocking film by isotropic etching;
• forming a third insulating film on said substrate and said first gate electrode;
• forming a second gate electrode on said third insulating film on at least said first gate electrode and a portion of said substrate adjacent thereto;
• and
• injecting an impurity of the second conductivity type into said substrate, using said second gate electrode as a mask.

A method of manufacturing a floating gate type non-volatile memory cell having an offset region, comprising the steps of:

• providing a semiconductor substrate;
• forming a first insulating film on said semiconductor substrate;
• forming a conductive layer on said first insulating film;
• forming a second insulating film on said conductive layer;
• patterning said second insulating film and said conductive layer to form a first gate electrode having a remaining portion of said second insulating film on an upper surface thereof;
• forming a masking layer having a first opening adjacent a first sidewall of said floating gate and a second opening spaced from a second sidewall of said floating gate;
• injecting an impurity into said semiconductor substrate through said openings in said masking layer;
• removing said masking layer;
• forming sidewall films on said first and second sidewalls of said first gate electrode, a lateral extent of said sidewall films defining an offset region;
• injecting an impurity into said substrate using said sidewall films and said first gate as a mask;
• removing said sidewall films;
• forming a third insulating film over a portion of said substrate including said offset region;
• forming a polysilicon layer on a resulting structure;
• patterning said polysilicon layer to form a second gate electrode;
• and
• injecting ions into said semiconductor substrate using said second gate electrode as a mask.