Dynamic latch circuit

#This invention relates to a dynamic latch circuit of a semiconductor integrated circuit, and more particularly to, a dynamic latch circuit having a multilayer structure of more than three interconnection layers.

#A dynamic latch circuit of a semiconductor integrated circuit generally consists of a clocked inverter and an inverter, or a transfer gate and an inverter.

#A first conventional dynamic latch circuits is composed of a clocked inverter and an inverter connected through a holding line to the clocked inverter. In this conventional dynamic latch circuit, when an input signal is supplied to the clocked inverter, the input signal is inverted based on the timing of a clock signal applied to the clocked inverter, so that the inverted signal is supplied on the holding line to be connected to the inverter. Thus, an output signal which is obtained by inverting the inverted signal is generated on an output line of the inverter.

#The invention will be explained in more detail in conjunction with appended drawings; wherein:

#FIG. 1A is a plan view showing a first conventional dynamic latch circuit;

#FIG. 1B is a sectional view taken on line Y--Y' of FIG. 1A;

#Before describing a dynamic latch circuit according to the invention, the conventional dynamic latch circuits briefly described before will be explained in conjunction with FIGS. 1A, 1B and 2 to 5.

#In FIGS. 1A and 1B, a first conventional dynamic latch circuit includes a semiconductor substrate 10 having a diffused layer 14 formed thereon, first to third interconnection layers 16, 18 and 20 formed on the semiconductor substrate 10, and insulating layers 22, 24, 26 and 28 by which the interconnection layers 16, 18 and 20 are insulated, respectively. The first to third interconnection layers 16, 18 and 20 are connected with a plurality of contact regions 12, respectively. The first interconnection layer 16 includes a first interconnection line 30 which is an input line of an inverter, an input line 32 of the dynamic latch circuit, and clock lines .phi. and .phi. each supplying a clock pulse to a clocked inverter. The second interconnection layer 18 includes a second interconnection line 34 which is an output line of the clocked inverter. The second interconnection line 34 is designed to be as short as possible to decrease a coupling capacity with other interconnection lines. The third interconnection layer 20 includes an output line 36 of the latch circuit.

#FIG. 2 shows an equivalent circuit of the dynamic latch circuit shown in FIGS. 1A and 1B. The dynamic latch circuit includes a clocked inverter composed of two P-channel transistors P1 and P2 and two N-channel transistors N1 and N2 connected in series between a power supply and ground, respectively, and an inverter composed of a P-channel transistor P3 and an N-channel transistor N3 connected in series between a power supply and ground, respectively. In the clocked inverter, gates of the P-channel transistor P2 and the N-channel transistor N1 are connected with the clock lines .phi. and .phi., respectively, and a common gate of the P-channel transistor P1 and the N-channel transistor N2 is connected with the input line IN(32). An output line of the clocked inverter (P1, P2, N1 and N2) is connected to a common gate of the P-channel transistor P3 and the N-channel transistor N3 through a holding line composed of the first and second interconnection lines 30 and 34, and an output line of the inverter (P3 and N3) is connected to the output line OUT(36).