Method of etching SiO.sub.2 dielectric layers using chemical mechanical polishing techniques
AssigneeMicron Technology, Inc.
InventorTrung T. Doan
Life of this patent
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Abstract
A method of planarizing SiO.sub.2 containing dielectric in semiconductor wafer processing comprising: a) providing a layer of undoped SiO.sub.2 atop a wafer; b) depositing a layer of borophosphosilicate glass atop the layer of undoped SiO.sub.2 ; and c) chemical mechanical polishing the borophosphosilicate glass layer selectively relative to the underlying layer of undoped SiO.sub.2 layer and using the layer of undoped SiO.sub.2 as an effective chemical mechanical polishing end-point etch stop to prevent further etching of the borophosphosilicate glass and produce a substantially planar upper wafer surface of dielectric.
Claims7
A method of planarizing SiO.sub.2 containing dielectric in semiconductor wafer processing comprising the following steps:
- providing a layer of undoped SiO.sub.2 atop a wafer;
- depositing a layer of borophosphosilicate glass atop the layer of undoped SiO.sub.2 ;
- chemical mechanical polishing the borophosphosilicate glass layer using a slurry composition which provides significant selectivity to the underlying layer of undoped SiO.sub.2 and using the layer of undoped SiO.sub.2 as an effective chemical mechanical polishing end-point etch stop to prevent further etching of the borophosphosilicate glass and produce a substantially planar upper wafer surface of dielectric, the slurry composition having a pH from about 7 to about 12 and having a solids concentration of from about 1% to 20% by weight.
Dependencies are inferred from the claim text.