US 4,908,688 AGranted

Means and method for providing contact separation in silicided devices

AssigneeMotorola, Inc.

InventorsClarence A. Lund, Richard R. Hamzik

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Abstract

A means and method for providing platinum or tungsten silicide contacts to source, drain, gate and tub regions of a dielectrically isolated MOSFET is described. A "false" gate is used to provide automatic self-aligned separation of the source-drain contact and the tub contact. An intermetallic forming material is uniformly coated over the doped substrate on which the gate and false gate region have been formed in a spaced-apart fashion. Upon heating the intermetallic forming layer reacts with the substrate and the polysilicon gates to form intermetallic regions. The remaining portion of the intermetallic forming layer is differentially etched away from the dielectric isolation walls and the sidewall oxides on either side of the gate and false gate. Alernatively, selective deposition may be used to avoid deposition on the dielectric regions. The false gate extends laterally across the isolation tub. This procedure separates the device contacts from the tub contact without the use of separate masking layers. A more compact structure is obtained.

Claims5

Dependent claims

An MOS device structure comprising:

a semiconductor substrate of a first conductivity type having therein a first part for containing an MOS device;
an isolation means substantially laterally surrounding the first part of the substrate and having first and second opposed portions joined by third and fourth opposed portions;
a first doped region of a second, opposite, conductivity type, located in the first part extending between the first and second portions of the lateral isolation means;
a second doped region of the second conductivity type, located in the first part separated from the first doped region by a channel region and extending between the first and second portions of the lateral isolation means;
an active gate on an insulator and self-aligned above the channel region;
a third doped region of the first conductivity type, located in the first part separated from the first doped region by an electrically inactive region and extending between the first and second portions of the lateral isolation means;
an inactive gate on an insulator and self-aligned above the inactive region;
and
an electrode shorting the inactive gate and the third doped region.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/132,822Filed 14 Dec 1987 · division
Priority: 14 Mar 1986
Granted: 13 Mar 1990
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10D 30/0223
Of FETs having insulated gates [IGFET]: having source and drain regions or source and drain extensions self-aligned to sides of the gate
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by
H10D
Inorganic electric semiconductor devices