Complementary semiconductor device having a double well
AssigneeHitachi, Ltd.
InventorYoshio Sakai
Life of this patent
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Abstract
A CMOSLSI is disclosed which includes a semiconductor body, a first N-well region formed in the semiconductor body, a second N-well region, a greater part of which is formed in the first N-well region, a first P-well region formed in the semi-conductor body, a second P-well region, a greater part of which is formed in the first P-well region, a P-channel MOS transistor formed in the second N-well region, and an N-channel MOS transistor formed in the second P-well region, to reduce the distance between the P-channel MOS transistor and the N-channel MOS transistor, thereby increasing the packing density of the CMOSLSI.
Claims30
A complementary semiconductor device including an insulated gate field effect transistor of a second conductivity type having a first deep well region of a first conductivity type formed in the surface of a semiconductor substrate and an insulated gate effect transistor of the first conductivity type having a second deep well region of the first conductivity type formed in the surface of the semiconductor substrate, wherein a third well region of the second conductivity type, smaller in depth than the second well region, is formed in the semiconductor substrate by the doping of an impurity from a surface area of the second well region defined by a window in one part of an insulating film for element separation which is also used for doping of a highly doped layer having a second conductivity type, and the highly-doped diffusion layer of the first conductivity type, smaller in depth than the third well region, is formed in the third well region by doping in the third well region with an impurity from the window on the second well region, said highly doped layer of the first conductivity type to be used as the source and drain regions of the insulated gate field effect transistor of the first conductivity type, and wherein a fourth well region of the first conductivity type, smaller in depth than the first well region, is formed in the semiconductor substrate by the doping of an impurity from a surface area of the first well region defined by a window in another part of the insulating film for element separation which is also used for doping of a highly doped layer of a second conductivity type, and the highly-doped diffusion layer of the second conductivity type, smaller in depth than the fourth well region, is formed in the fourth well region with an impurity from the window on the first well region, said highly doped layer of the second conductivity type to be used as the source and drain regions of the insulated gate field effect transistor of the second conductivity type, and a vertical bi-polar transistor having a base region formed from one of the third and fourth well regions is a circuit element.
A semiconductor memory comprising:
- a semiconductor body;
- a first N-well region formed in the semiconductor body;
- a second N-well region, a greater part of which is formed in the first N-well region, and wherein the second N-well region is defined by a window in one part of an insulating film for element separation which is also used for doping of a highly doped layer of P-type conductivity;
- a first P-well region formed in the semiconductor body;
- a second P-well region, a greater part of which is formed in the first P-well region, and wherein the second P-well region is defined by a window in another part of the insulating film for element separation which is also used for doping of a highly doped layer having N-type conductivity;
- a P-channel MOS transistor formed in the second N-well region;
- an N-channel MOS transistor formed in the second P-well region;
- and
- a memory cell formed in the semiconductor body in a third P-well region formed in the semiconductor body, the third P-well region having the same depth as the second P-well region.
A semiconductor device comprising:
- a semiconductor body;
- a first N-well region formed in the semiconductor body;
- a second N-well region, a greater part of which is formed in the first N-well region and wherein the second N-well region is defined by a window in one part of an insulating film for element separation which is also used for doping of a highly doped layer of P-type conductivity;
- a P-channel MOS transistor formed in the second N-well region;
- an N-channel MOS transistor formed in the second P-well region;
- an isolation region formed between the second N-well region and the second P-well region;
- and
- a memory cell that forms a semiconductor memory, the memory cell being formed in a third P-well region formed in the semiconductor body, the third P-well region having the same depth as the second P-well region.
A semiconductor memory comprising:
- a semiconductor body;
- a first N-well region formed in the semiconductor body;
- a second N-well region, a greater part of which is formed in the first N-well region;
- a first P-well region formed in the semiconductor body;
- a second P-well region, a greater part of which is formed in the first P-well region;
- a P-channel MOS transistor formed in the second N-well region;
- an N-channel MOS transistor formed in the second P-well region;
- and
- a memory cell formed in the semiconductor body, wherein the memory cell is formed in a third P-well region formed in the semiconductor body, and the third P-well region and the second P-well region have substantially the same depth.
A semiconductor device comprising:
- a semiconductor body;
- a first N-well region formed in the semiconductor body;
- a second N-well region, a greater part of which is formed in the first N-well region;
- a first P-well region formed in the semiconductor body;
- a second P-well region, a greater part of which is formed in the first P-well region;
- a P-channel MOS transistor formed in the second N-well region;
- an N-channel MOS transistor formed in the second P-well region;
- and
- an isolation region formed between the second N-well region and the second P-well region, wherein the semiconductor device further comprises a memory cell to form a semiconductor memory, and wherein the memory cell is formed in a third P-well region formed in the semiconductor body, and the third P-well region is substantially equal in depth to the second P-well region.
Dependencies are inferred from the claim text.