Dynamic random access memory trench capacitor

A dynamic random access memory having a trench capacitor, comprising:

• a semiconductor substrate of one conductivity type;
• a buried layer of the other conductiity type formed in said semiconductor substrate;
• a semiconductor layer formed on said semiconductor substrate having said buried layer;
• a trench extending through said semiconductor layer and reaching the buried layer of the other conductivity type;
• an insulating layer formed on an inner side surface of said trench;
• a first conductive layer formed on said insulating layer formed on said trench and having a lower portion ohmically connected to said buried layer, an upper end of said first conductive layer being located lower than a top level of said trench for preventing said first conductive layer from being exposed outside said trench;
• a dielectric layer formed on said first conductive layer on the inner surface of said trench;
• a second conductive layer filled in said trench and formed on said dielectric layer;
• said first conductive layer, said dielectric layer, and said second conductive layer constituting a charge storage capacitor;
• and
• a MIS transistor for switching charging or discharging of said charge storage capacitor,
• wherein said second conductive layer is ohmically connected to one of source and drain regions of said MIS transistor, and said first conductive layer is supplied, through said buried layer of the other conductivity type, with a bias voltage different from that supplied to said semiconductor substrate.

A dynamic random access memory having a trench capacitor, comprising:

• a semiconductor substrate of one conductivity type;
• a trench formed in said semiconductor substrate;
• an insulating layer formed on an entire inner side surface of said trench, said insulating layer having a thickness which allows a passage of carriers therethrough by a tunnel phenomenon;
• a first conductive layer formed on said insulating layer and maintained at the same potential as that of said semiconductor substrate through said insulating layer, an upper end of said first conductor layer being located lower than a top level of said trench for preventing said first conductive layer from being exposed outside said trench;
• a dielectric layer formed on said first conductive layer;
• a second conductive layer of the other conductivity type filled in said trench and formed on said dielectric layer,
• said first conductive layer, said dielectric layer, and said second conductive layer constituting a charge storage capacitor;
• and
• a MIS transistor formed in said semiconductor substrate,
• wherein said second conductive layer of said charge storage capacity is ohmically connected to a source or drain region of said MIS transistor.