Electrically-erasable/programmable nonvolatile semiconductor memory device

Abstract

In an electrically-erasable/programmable nonvolatile semiconductor memory device according to the invention, a one-bit memory cell is constituted by a series circuit of a selecting MOS transistor and a data storage MOS transistor. A floating gate electrode and a control gate electrode are formed in the data storage MOS transistor, One portion of the floating gate electrode is formed on a channel region of the data storage MOS transistor through a gate insulating film. The other portion of the floating gate electrode is formed on a drain region of the data storage MOS transistor through a gate insulating film, a portion of which is sufficiently thinner than the gate insulating film. One and the other portions of the floating gate electrode are structurally separated from each other but are electrically connected with each other on a field region. A control gate electrode having substantially the same shape as that of the floating gate electrode is formed thereon through a gate insulating film.

Dependencies are inferred from the claim text.