Method for the manufacture of bipolar transistor structures with self-adjusting emitter and base regions for extreme high frequency circuits

A method for the manufacture of bipolar transistor structures with self-adjusting emitter-base regions for extreme high frequency circuits wherein both the emitter region and the base region in a silicon semiconductor substrate are generated by an out-diffusion of doped polysilicon layers deposited directly on the substrate, the emitter region being centrally generated in the base region by masking and insulating silicon oxide layers such that an active base zone arises uder the emitter region along with an inactive base zone symmetrical thereto, and wherein dry etching methods producing vertical etching profiles are employed for structuring the silicon oxide and polysilicon layers, comprising the steps of:

• (a) structuring a first silicon oxide layer on the silicon substrate such that a region to be used for the base region is exposed at a surface of the substrate;
• (b) depositing a first polysilicon layer and implanting the layer with ions up to a maximum depth corresponding to half of the first polysilicon layer thickness;
• (c) depositing a second silicon oxide layer;
• (d) executing a photoresist process for defining the base region and the emitter region lying in the base region;
• (e) executing an anisotropic, reactive ion etching process for removal of the second silicon oxide layer not covered by the photoresist mask;
• (f) executing an anisotropic, reactive ion etching process for removal of the first polysilicon layer not covered by the second silicon oxide layer to such degree that a maximum of about 100 nm of the first polysilicon layer remains on the substrate surface;
• (g) generating a third silicon oxide layer for manufacture of an edge insulation by oxidation of the remaining polysilicon layer;
• (h) depositing a fourth silicon oxide layer on the third silicon oxide layer for broadening of the edge insulation;
• (i) executing an anisotropic, reactive etching process without a mask for removal of said fourth silicon oxide layer with the exception of the edge insulation and for the removal of said third silicon oxide layer in the emitter region such that a ratio of a vertical etching rate to a lateral etching rate >5:1 and a ratio of an oxide etching rate to a silicon etching rate >15:1;
• (j) depositing and structuring a second doped polysilicon layer in the emitter region;
• (k) executing a thermal treatment for activation of the emitter region;
• and
• (l) providing contacts to the polysilicon regions connecting to the base and emitter regions.