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US 4,539,580 AGranted
High density integrated circuit device with MOS transistor and semiconductor region having potential wells
AssigneeTokyo Shibaura Denki Kabushiki Kaisha
InventorJunichi Matsunaga
Life of this patent
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Abstract
A semiconductor device includes a dynamic memory area formed in a semiconductor substrate and set in an inequilibrium potential state, and a plurality of MOS transistors which emit minority carriers or more than a predetermined number into said semiconductor substrate during operation in a saturation region. Each of the MOS transistors is so arranged that a prolonged line extending in a direction from the source region to the drain region may cross the dynamic memory area.
Claims7
A semiconductor device comprising:
- a semiconductor substrate;
- a semiconductor region formed within said semiconductor substrate and having a potential locally susceptible to change by minority carriers;
- and
- at least one MOS transistor having source and drain regions and which emits minority carriers of more than a predetermined number into said semiconductor substrate during operation in a saturation region, wherein said semiconductor region is arranged in an area defined by two boundary lines which start from said MOS transistor and form angles of substantially .+-.45.degree. with respect to a line connecting said source and drain regions, and wherein the material connecting said semiconductor region and said MOS transistor is semiconductor material of uniform conductivity type.
1 more element
A semiconductor device comprising:
- a semiconductor substrate;
- a semiconductor region formed within said substrate and having a potential locally susceptible to change by minority carriers;
- and
- at least one MOS transistor having source and drain regions and which emits minority carriers of more than a predetermined number into said semiconductor substrate during operation in a saturation region, wherein said semiconductor region is of substantially rectangular shape and is arranged in an area defined by two boundary lines which start from said MOS transistor and form angles of substantially .+-.45.degree. with respect to a line connecting said source and drain regions, said at least one MOS transistor being arranged with said two boundary lines being substantially parallel to two sides of said semiconductor region.
1 more element
Dependencies are inferred from the claim text.