Nonvolatile semiconductor memory device
AssigneeTokyo Shibaura Denki Kabushiki Kaisha
InventorsHiroshi Iwahashi, Masamichi Asano
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Abstract
In a nonvolatile semiconductor memory device using as memory cells insulated-gate type field effect transistors each having source and drain regions, a floating gate electrode, and a control gate electrode, the width of the floating and control gate electrodes is narrower at those portions which are located over a channel between the source and drain regions in each memory cell than at those portions which are not located over the channel.
Claims3
A nonvolatile semiconductor memory device, comprising:
- a semiconductor substrate of a preselected conductivity type;
- a drain region formed on said semiconductor substrate, said drain region having first and second oppositely disposed end portions and a contact hole substantially midway between said end portions;
- first and second source regions formed on said semiconductor substrate adjacent but spaced apart from said first and second end portions of said drain region, respectively, by a predetermined distance;
- first and second channel regions formed, respectively, between said first end of said drain region and said first source region, and between said second end of said drain region and said second source region;
- a first gate insulation film overlying said first and second channel regions;
- first and second floating gate electrodes formed on said first gate insulation film and overlying, respectively, said first and said second channel regions;
- a second gate insulation film overlying said first and second floating gate electrodes;
- and
- first and second control gate electrodes formed on said second gate insulating film and overlying entirely said first and second floating gate electrodes, respectively,
- wherein the width dimension of each of said floating gate electrodes and said control gate electrodes is narrower at portions thereof located directed over said channel regions, than at portions thereof which are not located directly over said channel regions.
A nonvolatile semiconductor memory device according to claim 5 wherein said portions of said first floating gate electrode and said first control gate electrode not located over said first channel region extend towards said portions of said second floating electrode and second control gate electrode not located over said first channel region.
Dependencies are inferred from the claim text.