US 4,363,696 AGranted

Short circuit prevention in the manufacture of semiconductor devices

AssigneeTokyo Shibaura Denki Kabushiki Kaisha

InventorsYoshihide Nagakubo, Hisakazu Iizuka

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Abstract

A first level interconnection layer of substantially a given width is formed on an insulating film on a semiconductor substrate. At least two second level interconnection layers, which cross the first level interconnection layer on another insulating layer, are formed. In a step for forming the first level interconnection layer, projections are formed at each side of the first level interconnection layer between the crossings of the second level interconnection layers. The total width of the first level interconnection layer including the width of the projection is larger than the given width. After the second level interconnection layers are formed, the projections of the first level interconnection layer are removed along with any second level interconnection layer material remaining intermediate the second level interconnection layers, thereby to prevent short-circuiting between the second level interconnection layers.

Claims13

Dependent claims

A manufacturing method of semiconductor devices including a step for forming at least one first interconnection layer with a given width on a first insulating layer and a step for forming at least two second interconnection layers which cross said first interconnection layer on a second insulating layer, said manufacturing method comprising:

a first step for forming an underlying interconnection layer including said first interconnection layer on said first insulating layer, said underlying interconnection layer having projected portions at both sides of said interconnection layer of said given width, at least a part of each projected portion being removed subsequently;
a second step for selectively etching said first insulating layer with said underlying interconnection layer as a mask;
a third step for forming said second insulating layer;
a fourth step for forming a conductive layer on the entire surface, including said underlying interconnection layer, for forming said second interconnection layers;
a fifth step for covering said second interconnection layers with a first etching resist layer;
a sixth step for removing said conductive layer covering said entire surface, except in that region corresponding to said second interconnection layers, by an anisotropic etching method with said first etching resist layer as a mask;
a seventh step for removing said second insulating layer with said second interconnection layers as a mask, a part of said conductive layer remaining under the side edges of said projected portions, causing short-circuiting between said second interconnection layers through said conductive layer;
an eighth step for forming a second etching resist layer on said underlying interconnection layer, said second etching resist layer being provided between said second interconnection layers and at such a position as to cause said remaining conductive layer in said seventh step to be removed by an anisotropic etching method with said second etching resist layer as a mask, thereby preventing the short-circuiting between said second interconnection layers;
a ninth step for removing a part of said underlying interconnection layer by said anisotropic etching method with said etching resist layer as a mask, to finally form said first interconnection layer having substantially said given width;
and
a tenth step for removing said second etching resist layer formed in said eighth step.

8 more elements

A method of manufacturing semiconductor devices, wherein at least one first interconnection layer of a given width is formed on a first insulating layer and at least two second interconnection layers crossing the first interconnection layer are formed over a second insulating layer, the manufacturing method comprising:

a. laying down said first interconnection layer at a greater width than said given width at predetermined locations thus forming projecting portions on both sides of said given width;
b. etching said first insulating layer to a predetermined depth with said laid down first interconnection layer as a mask;
c. forming said second insulating layer covering the exposed surfaces of said laid down interconnection layer;
d. forming a conductive layer over the entire upper surface, including said first and second insulating layers, for forming from portions thereof said second interconnection layers;
e. covering said conductive layer with a first etching resist layer only in the areas defining said second interconnection layers;
f. etching by an anisotropic etching method said conductive layer with said first etching resist layer as a mask, producing said second interconnection layers;
g. removing said second insulating layer using said second interconnection layers as masks;
h. forming on said laid down first interconnection layer between said second interconnection layers a second etching resist layer of said given width, leaving exposed said projecting portions of said laid down first interconnection layer;
i. etching by an anisotropic etching method, with said second etching resist layer as a mask, said projecting portions of said laid down interconnection layer and any of said conductive layer remaining between said second interconnection layers after said anisotropical etching of said conductive layer;
and
j. removing said second etching resist layer.

8 more elements

Dependencies are inferred from the claim text.