Large scale semiconductor integrated circuit device

An LSI chip comprising:

• a semiconductor substrate having a planar surface;
• transistors and resistors formed with selected patterns in said surface;
• metallic layers on said surface comprising means for selectively connecting said transistors and resistors;
• input/output terminal pads disposed at the periphery of said LSI chip, said pads including terminal pads for supply and ground potentials for operating said LSI chip;
• large transistors connected as emitter-follower circuits for outputting signals from internal logic circuits of said LSI chip, said large transistors being located near said input/output terminal pads;
• macros arranged in an array on said surface, each said macro selectively comprising said transistors and resistors to form a respective unit logic circuit, each said unit logic circuit selectively handling high and low power, said macros comprising said unit logic circuits for handling high power being selectively terminated internally and externally of said LSI chip, said macros comprising said unit logic circuits for handling low power being terminated only within said LSI chip, said transistors and resistors of said macros comprising said unit logic circuit for handling high power having dimensions that are selectively larger than the corresponding dimensions of said transistors and resistors of said macros comprising said unit logic circuits for handling low power, said macros comprising said unit logic circuits for handling high power being located at the periphery of said macro array.