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US 4,225,876 AGranted
Monolithically integrated semiconductor arrangement
AssigneeSiemens Aktiengesellschaft
InventorKarlheinrich Horninger
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AssigneeSiemens Aktiengesellschaft
InventorKarlheinrich Horninger
Estimating the term…
A monolithically integrated semiconductor arrangement is disclosed wherein a plurality of first lines are provided which run parallel to one another and which are provided with first terminals at one end. A plurality of second lines which run parallel to one another are also provided which cross beneath the first lines and are connected via load elements at one end to a supply voltage terminal. Reference potential lines are also provided adjacent each of the second lines. At a series of selected crossing points of the first and second lines coupling elements are formed which can be operated by the first line and by which the second line is connected to an adjacent reference potential line. The semiconductor arrangement is formed on a semiconductor layer having a thin insulating layer thereon with the second lines and reference potential lines arranged on the thin insulating layer. The first lines are then arranged over the second line and reference potential lines and are separated therefrom by an additional insulating layer. At crossing points selected for coupling, a portion of the first line approaches the semiconductor layer surface more closely and is separated therefrom by the thin insulating line. Diffusion zones are provided at one end of each of the reference potential lines and second lines. With the system disclosed, diffusions are not required for the formation of the first and second lines and coupling elements.
A monolithically integrated semiconductor arrangement comprising:
A method for operating a semiconductor arrangement as a fixed word store (Read Only Memory), said arrangement having a plurality of first lines which run parallel to one another and are provided with end-side first terminals, a plurality of second lines which run parallel to one another crossing beneath the first lines and are connected at one end by load elements to a supply voltage terminal, second terminals being provided at a connection of the second lines to the load elements, a plurality of reference potential lines adjacent the second lines, a series of selected crossing points of the first and second lines forming a coupling element operable by the first line and by which the second line can be connected to an adjacent reference potential line, said first and second lines comprising conductive strips separated by insulating means from one another and a semiconductor layer surface, comprising the steps of:
A method for operating a semiconductor arrangement as a decoder circuit, said arrangement having a plurality of first lines which run parallel to one another and are provided with end-side first terminals, a plurality of second lines which run parallel to one another crossing beneath the first lines and are connected at one end by load elements to a supply voltage terminal, second terminals being provided at a connection of the second lines to the load elements, a plurality of reference potential lines adjacent the second lines, a series of selected crossing points of the first and second lines forming a coupling element operable by the first line and by which the second line can be connected to an adjacent reference potential line, said first and second lines comprising conductive strips separated by insulating means from one another and a semiconductor layer surface, comprising the steps of:
A method for operating a semiconductor arrangement as a matrix within a programmable logic arrangement, said semiconductor arrangement having a plurality of first lines which run parallel to one another and are provided with end-side first terminals, a plurality of second lines which run parallel to one another crossing beneath the first lines and are connected at one end by load elements to a supply voltage terminal, second terminals being provided at a connection of the second lines to the load elements, a plurality of reference potential lines adjacent the second lines, a series of selected crossing points of the first and second lines forming a coupling element operable by the first line and by which the second line can be connected to an adjacent reference potential line, said first and second lines comprising conductive strips separated by insulating means for one another and a semiconductor layer surface, comprising the steps of:
A monolithically integrated semiconductor arrangement, comprising:
Dependencies are inferred from the claim text.