Back to results
US 4,062,037 AGranted
Semiconductor memory device
AssigneeFujitsu Limited
InventorsRyoiku Togei, Akira Takei, Kunihiko Wada
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device, which comprises: a P-type semiconductor material comprising on the surface thereof, an N-type doped layer, one surface region of the substrate adjoining the doped layer being used as a gate region, and further comprising in the interior thereof an N-type buried layer below another surface region of said substrate adjoining said one surface region. Electric charges representing information are stored in the buried layer. The reading time and the refreshing period are improved by shortening said reading time and lengthening said refreshing time utilization of said N-type buried layer.
Claims22
A semiconductor memory device, which comprises:
- a semiconductor material substrate having one particular conductivity type and comprising, on the surface thereof, a doped layer with an impurity of the opposite conductivity type, a first surface region of said substrate adjoining said doped layer used as a gate region, a second surface region of said substrate adjoining said first surface region used as a memory cell region, and further comprising in the interior thereof a buried layer of said opposite conductivity type situated below said memory cell region of said substrate;
- a doped layer electrode disposed on said substrate and electrically connected with said doped layer;
- a first insulating layer placed on said substrate and, with said doped layer electrode, incompletely covering said doped layer so as to form an aperture exposing a part of said doped layer;
- a gate electrode placed over said gate region and electrically insulated from said gate region by at least said first insulating layer;
- and
- a memory cell electrode placed over said memory cell region and electrically insulated from said memory cell region by at least said first insulating layer;
- wherein an electric charge of said opposite conductivity type is either injected from said doped layer through said gate region into said buried layer to be stored in this layer or withdrawn from said buried layer through said gate region to said doped layer, depending upon the electric potential levels in said substrate, which levels are established by electric fields created by each of said electrodes through said insulating layers.
4 more elements
In a semiconductor memory device which includes:
- a semiconductor material substrate having one particular conductivity type and comprising, on a given surface thereof, a doped layer with an impurity of conductivity type opposite to said one particular conductivity type, and further comprising a first surface region adjoining said doped layer and defining a gate region, and a second surface region adjoining said first surface region remote from said doped layer and defining a memory cell region;
- a insulating layer disposed on said substrate over said gate region and said memory cell region, and incompletely covering said doped layer so as to form an aperture exposing a portion of said doped layer;
- a gate electrode disposed on said insulating layer, and overlying said gate region;
- and
- a memory cell electrode disposed on said insulating layer, and overlying said memory cell region;
- the improvement comprising the inclusion, within the interior of said substrate in said memory cell region, of a buried layer of said conductivity type opposite to said one particular conductivity type.
3 more elements
A method of storing information in a semiconductor memory device, comprising the steps of:
- a. providing a semiconductor material substrate of given conductivity type and having, on a given surface thereof, a doped layer with a lead electrode disposed thereon and connected thereto, and having, disposed above said given surface, a gate electrode adjacent to said doped layer, and a memory cell electrode adjacent to said gate electrode, and having, within the interior of said substrate below said memory cell electrode, a buried layer of conductivity opposite to said given conductivity;
- b. applying a first set of respective voltage pulses to said memory cell electrode, said gate electrode and said lead electrode, respectively, during a first time period so as to cause the electric charge in said doped layer to move through a region near the surface of said substrate in a horizontal direction until said charge is under said memory cell electrode;
- and
- c. applying a second set of respective voltage pulses to said memory cell electrode, said gate electrode and said lead electrode, respectively, during a second time period so as to cause said charge to move vertically into said buried layer.
1 more element
A method of reading information from a semiconductor memory device, comprising the steps of:
- a. providing a semiconductor material substrate of given conductivity type and having, on a given surface thereof, a doped layer with a lead electrode disposed thereon and connected thereto, and having, disposed above said given surface, a gate electrode adjacent to said doped layer, and a memory cell electrode adjacent to said gate electrode, and having, within the interior of said substrate below said memory cell electrode, a buried layer of conductivity opposite to said given conductivity;
- and
- b. applying a set of respective voltage pulses, to said memory cell electrode, gate electrode, and lead electrode, respectively, so as to cause an electric charge previously stored in said buried layer to move from said buried layer to an underlying region of said gate electrode and then to move through a region near the surface of said substrate in a horizontal direction.
Dependencies are inferred from the claim text.