Semiconductor device structure and methods of forming the same

A semiconductor device structure, comprising:

• a first active region and a second active region comprising first and second respective channel regions and first and second respective source/drain regions adjacent to the first and second respective channel regions;
• a gate structure over the first and second respective channel regions;
• first and second respective source/drain features over the first and second respective source/drain regions;
• a source/drain contact electrically coupled to one of the first or second respective source/drain features by way of a metal silicide layer;
• a first isolation region and a second isolation region disposed between the first active region and the second active region;
• a semiconductor substrate portion disposed between the first isolation region and the second isolation region, wherein the first isolation region and the second isolation region comprise a nitride-containing material;
• and
• an interlayer dielectric (ILD) layer disposed over the first and second respective source/drain features, wherein the source/drain contact is disposed in the ILD layer, and wherein an electrical conductivity of the metal silicide layer is between an electrical conductivity of the first and second respective source/drain features and an electrical conductivity of the source/drain contact, wherein the metal silicide layer comprises a curved profile.

A method, comprising:

• forming an active region;
• forming an isolation region alongside the active region, wherein the isolation region includes a first shallow trench isolation (STI) region adjacent the active region in a first direction and a second STI region spaced from the first STI region in the first direction such that the first STI region is between the active region and the second STI region, and wherein the first STI region and the second STI region are separated by a semiconductor substrate portion;
• forming a sacrificial gate structure over the active region;
• forming a source/drain feature;
• forming a contact etch stop layer on the semiconductor substrate portion;
• forming an interlayer dielectric (ILD) layer over the contact etch stop layer;
• removing the sacrificial gate structure;
• forming a gate structure over the active region, wherein the gate structure comprises an interfacial layer, a gate dielectric layer over the interfacial layer, and at least one metal layer over the gate dielectric layer, wherein the interfacial layer interfaces the active region, wherein the gate dielectric layer and the isolation region intermix at an interface between the gate dielectric layer and the isolation region;
• forming a source/drain contact disposed in the ILD layer to electrically couple to the source/drain feature;
• and
• forming a metal silicide layer between the source/drain feature and the source/drain contact, wherein an electrical conductivity of the metal silicide layer is between an electrical conductivity of the source/drain feature and an electrical conductivity of the source/drain contact, wherein the metal silicide layer comprises a curved profile.