Standard cell architecture with frontside and backside connections

An electronic device, comprising:

• a chip package comprising one or more dies, at least one of the one or more dies comprising
• a semiconductor device having a semiconductor region extending from a source or drain region in a first direction and a gate structure extending over the semiconductor region in a second direction substantially orthogonal to the first direction;
• a dielectric layer beneath the gate structure, the dielectric layer having a thickness of less than 50 nm;
• a backside conductive contact adjacent to the dielectric layer along the second direction and on a bottom surface of the source or drain region;
• and
• a topside conductive contact on a top surface of the source or drain region.

An integrated circuit comprising:

• a first semiconductor region extending from a first source or drain region in a first direction;
• a second semiconductor region extending from a second source or drain region in the first direction;
• a gate structure extending over the first semiconductor region and the second semiconductor region in a second direction different from the first direction;
• a dielectric layer beneath the gate structure;
• a backside conductive contact extending through the dielectric layer to contact a bottom surface of the first source or drain region;
• and
• a topside conductive contact on a top surface of the first source or drain region,
• wherein a pitch along the second direction between the first semiconductor region and the second semiconductor region is between 20 nm and 80 nm.