Semiconductor structure and manufacturing method thereof

A method, comprising:

• forming a peripheral circuit and memory cells in a memory array arranged in rows and columns over a substrate, the substrate defining a near-end bit-line region, a far-end bit-line region, a transition region between the near-end and far-end bit-line regions, a cell edge region, wherein in a top view, the cell edge region is between the near-end bit-line region and the peripheral circuit, and the near-end bit-line region is between the far-end bit-line region and the cell edge region;
• forming first far-end bit-line segments extending in a first metal layer over the far-end bit-line region to the transition region, the first far-end bit-line segments electrically coupled to a first subset of the memory cells in the columns of the memory array within the far-end bit-line region;
• forming transition segments in a second metal layer at the transition region, the transition segment electrically coupled to the first far-end bit-line segments, respectively;
• forming second far-end bit-line segments extending in a third metal layer over the near-end bit-line region to the cell edge region, the second far-end bit-line segments electrically coupled to the transition segments, respectively, and electrically isolated from a second subset of the memory cells in the columns of the memory array within the near-end bit-line region;
• and
• forming metal structures in the third metal layer at the cell edge region, wherein the metal structures connect the second far-end bit-line segments to bit-lines of the peripheral circuit, respectively, wherein the metal structures extend lengthwise along a direction parallel with a lengthwise direction of the second far-end bit-line segments, and have a width greater than a width of the second far-end bit-line segments.

A semiconductor structure, comprising:

• memory cells in a memory array arranged in rows and columns over a substrate, the substrate defining a near-end bit-line region, a far-end bit-line region, a transition region between the near-end and far-end bit-line regions, and a cell edge region, wherein the near-end bit-line region is between the transition region and the cell edge region;
• a near-end bit-line extending in a first metal layer over the near-end bit-line region to the cell edge region, the near-end bit-line electrically coupled to a first subset of the memory cells in one of the columns of the memory array within the near-end bit-line region;
• a far-end bit-line comprising:
• a first segment extending in the first metal layer over the far-end bit-line region to the transition region, the first segment electrically coupled to a second subset of the memory cells in the one of the columns of the memory array within the far-end bit-line region;
• and
• a second segment extending in a second metal layer over the near-end bit-line region to the cell edge region, the second metal layer being at a higher elevation than the first metal layer;
• a transition segment in a third metal layer at the cell edge region, the transition segment electrically coupled to the near-end bit-line and being at an elevation higher than the first metal layer and lower than the second metal layer;
• and
• a peripheral circuit adjacent to the cell edge region, the peripheral circuit comprising first and second bit-lines extending in the second metal layer,
• wherein the first bit-line of the peripheral circuit connects to the transition segment along a first continuous path in the second metal layer, and the second bit-line of the peripheral circuit connects to the second segment of the far-end bit-line along a second continuous path in the second metal layer.