Integrated circuit structure and method for forming interconnection structure of memory cell

A method comprising:

• forming a first level metal layer on a memory cell, the first level metal layer including a first bit-line conductor and a second bit-line conductor arranged along a first routing direction;
• forming a second level metal layer on the first level metal layer, the second level metal layer including a first word-line conductor extending along a second routing direction different from the first routing direction;
• forming a via line on the first word-line conductor, the via line extending along the second routing direction;
• and
• forming a third level metal layer on the second-level metal layer, the third level metal layer including a second word-line conductor extending along the second routing direction, and the second word-line conductor, the via line and the first word-line conductor overlapping along the second routing direction to form a double-layered word-line conductor.

A device comprising:

• a first word-line conductor, disposed at a first layer and extending along a routing direction;
• a via line disposed on the first word-line conductor and extending along the routing direction;
• and
• a second word-line conductor, disposed at a second layer above the first layer and extending along the routing direction, wherein the second word-line conductor, the via line and the first word-line conductor overlap along the routing direction.