Gate isolation features for memory and logic devices

A semiconductor structure, comprising:

• a substrate having a memory device region and a logic device region;
• a first gate structure and a second gate structure over the memory device region;
• a third gate structure and a fourth gate structure over the logic device region;
• a first gate isolation feature sandwiched between the first gate structure and the second gate structure;
• and
• a second gate isolation feature sandwiched between the third gate structure and the fourth gate structure,
• wherein a composition of the first gate isolation feature is different from a composition of the second gate isolation feature.

A method, comprising:

• providing a precursor structure that includes:
• a substrate comprising a first device region and a second device region,
• a first bottom gate structure over the first device region,
• a first top gate structure over the first bottom gate structure,
• a first hard mask layer over the first top gate structure,
• a second bottom gate structure over the second device region,
• a second top gate structure over the second bottom gate structure, and
• a second hard mask layer over the second top gate structure,
• forming a first trench through the first hard mask layer, the first top gate structure, and the first bottom gate structure;
• forming a second trench through the second hard mask layer, the second top gate structure, and the second bottom gate structure;
• depositing a first dielectric layer over the first device region and the second device region to fill the first trench and the second trench;
• forming a patterned mask over the first device region and the second device region while a portion of the first dielectric layer over the second trench is exposed through an opening of the patterned mask;
• etching the first dielectric layer in the second trench to form an inner trench;
• removing the patterned mask;
• depositing a second dielectric layer over the inner trench;
• and
• after depositing of the second dielectric layer, planarizing the precursor structure to expose top surfaces of the first top gate structure and the second top gate structure and to form a first gate cut feature in the first trench and a second gate cut feature in the second trench,
• wherein a composition of the first dielectric layer is different from a composition of the second dielectric layer.